With the European Conference on Optical Communication (ECOC) in full swing in Glasgow, Dr Adam Carter, CEO of OpenLight, talks to Nick Flaherty about 1.6Tbit/s links and generative AI in photonics.
The push for high speed interconnect in the data centre for AI is driving the advancement of photonic chip technology in several ways, says Carter.
“OpenLight has a very interesting business model as it allows access to designing silicon photonics through the foundry partners, today it is Tower, and then offer design as a service,” says Carter.
It was spun out of Juniper Networks last year with EDA tool giant Synopsys as a joint venture partner to commercialise the process development kit (PDK) and technology for building photonic chips. Carter joined OpenLight in January having worked at HP-Agilent-Avago-Broadcom, as well as networking giant Cisco’s transceiver module business (and competitor to Juniper) and photonics pioneer Oclaro before it was sold to Lumentum.
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“We design components for the PDK and validate those. Synopsys had very little experience in photonics and that’s why they came in as a major investor. Now its about growing the customer base and driving silicon photonics into other markets, not just communications,” he tells eeNews Europe.
“Everywhere a semiconductor laser is used you could use one of these circuits,” he said.
“The differentiation is we integrate the active elements into the silicon circuit, lasers, modulators, optical amplifiers and also detectors and photodiodes. There’s one other company that does the integrated components, and that’s Intel, but you can’t design the components.
“Today most people externally couple the lasers to a passive component. As the bandwidth and channel density goes up that is difficult to do and cost prohibitive for the automatic alignment and the power consumption with banks of lasers,” he explains. “One of the key advantages of the integration is much better coupling for lower power lasers. The difference can be 90% for us and 30% externally coupled lasers.”
“We work with startups to fortune 100 companies – we have a broad customer base, and where those customers are in the design pipeline is different. Some people have experience with passive components, others with the ASIC for the photonics.
The discussion at ECOC for 800G is around Coarse Wavelength Division Multiplexing (CWDM) which is already being used for the first 800G photonic chips.
“The CWDM variant of 800G we are showing at ECOC is important as this is a key building block for a CWDM 1.6T variant with two blocks and we will be showing 1.6Tbit/s at the OFC Conference in March in San Diego. We are testing a parallel version at 200G/channel now as we need to tie the laser driver availability into that as the analogue chipsets aren’t quite there yet.”
There is also a push to use generative AI to speed up the photonic hcip design process, just as it has in digital logic. Here the investment by Synopsys is key.
“We have added photonic measurement simulation to the Synopsys toolkit in the last version, and Synopsys has been talking about a ‘photonic.ai’ tool in investor meetings. That is probably the way this goes – the ability for someone to use AI to generate a chip, I’m all for it if it if it uses my PDK.”
This is significant as OpenLight is looking at more than just the datacomms market,
“There’s three major markets getting traction,” he says.
The first is the obvious datacentre market, with hyperscalar and AI providers wanting more connectivity between clusters, increasing the bandwidth per pluggable module from 400Gbit/s to 800Gbit/s and even higher. “There is 1.6Tbit/s to come and we do reference PICs and have an 8 x 100G DRA, and ECOC CWDM variant, and a 1.6Tbit/s version.”
There is also significant interest in LiDAR laser sensors for automotive and machine vision. “We have seen a lot of traction with integrated optical amplifiers for frequency modulated continuous wave (FMCW) and the more channels the better refresh pixel rate so our technology 16 channels with 16 SOA 5 x7 mm chip.
Photonic chiplet technology
Then there is the high speed optical interconnect for chiplets within a package. “For memory disaggregation chiplets will be more important Synopsys are developing IP in that area for what is the best partitioning of the design. The only place that might change is with Networks for AI as the optics will be greater at 1.6Tbit/s and 3.2Tbit/s. That will struggle to get into a small form factor pluggable module.”
Then there is photonic quantum computers which need a massive amount of scalable integrated photonic chips. “We are starting to see interest in the quantum side, and some have had access to the process so it is something that will develop, but its not something we are chasing,” he said.
OpenLight is looking to expand its foundry beyond the current relationship with Tower Semiconductor, including a supplier with 300mm wafers, but this can be a complicated change as the photonics process requires extra steps..
“A foundry relationship is usually strategic for the end customer and we ere working on how to expand our menu of foundry partners and our menu of test houses and packaging houses – that’s very interesting,” said Carter.
“We are working with another foundry on 300mm wafers and a lot of our Asian customers want Asian supply,” he said. “We do the III-V processing in the foundry so a lot of the work has to be done there, for example adding gold for the InP contact layer.”
The company has 50 people and this is ramping up as customers pay a license fee to get access to the PDK and the technology. “This is not an optical subassembly, it’s a photonic ASIC. This is an ASIC model with the optical components inside and we are supplying the building blocks.”