CEO interview: MIPS’ Sameer Wasson on a RISC-V reboot

CEO interview: MIPS’ Sameer Wasson on a RISC-V reboot

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By Peter Clarke

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MIPS Inc. is emerging as a significant RISC-V processor core licensor under its recently-appointed CEO Sameer Wasson. eeNews Europe interviewed Wasson to find out how he expects to navigate the choppy waters of a processor market in flux.

MIPS was founded in 1984 and was one of pioneers of the first RISC revolution in processor architecture. This carried the company through to the 1990s where it found itself opposite a UK startup called Arm. Arm’s focus on power efficiency enabled it to capture the smartphone market and large swathes of the general embedded markets. MIPS was more performance-oriented. It started out providing workstation processors and performed well in networking and communications. But eventually it went through a series of corporate acquisitions and sales before ending up being majority-owned by Tallwood Ventures with a remit to continue its processor core licensing business based on the RISC-V open-source architecture.

Wasson joined the company in September 2023 from Texas Instruments (see MIPS to drive RISC-V market penetration and innovation). There he was responsible for high-performance microcontrollers and processors. “I could see RISC-V has a lot of potential and that it provides an opportunity to give control back to engineers. I think of MIPS as 40 year-old startup, or a restartup. In fact, the company was already heading in the RISC-V direction since 2018-2019.”

Starting over

As a ‘restartup’ MIPS has the advantage of a royalty stream from existing licensees of its historical MIPS instruction set architecture (ISA) processor cores. It also gives a base of customer relations to stand on. As a private company MIPS does not have to reveal revenue details on a quarterly basis but Wasson said the company is at about a 50:50 split between MIPS ISA royalties and upfront licensing fees for MIPS upcoming high-performance RISC-V core, the P8700. Most RISC-V processor core providers are private companies making sales estimates difficult but Wasson reckons that MIPS is already one of the top two or three RISC-V licensors out there.

Wasson said the philosophy for MIPS is to take the things that the original MIPS ISA does well and recast them using the RISC-V base ISA and extensibility under RISC-V. This provides an upgrade path for existing MIPS licensees as well as a way in to certain applications for new customers.

“We don’t want to try and ‘boil the ocean’ and take on Arm. MIPS does some things well so we focus on those,” said Wasson. He gives the example of efficient data movement under the MIPS ISA which translated into successful licensing into networking and modems and into some automotive applications. “This capability we are translating into datacentre networking, traffic management, DPU applications,” Wasson said.

In the automotive case MIPS has been part of Mobileye’s offering over many generations of ADAS processor “We have Mobileye as a RISC-V customer and also a couple of hyperscalers, which we can’t name,” said Wasson. He added that the passage of time has made MIPS networking capability relevant to more applications.


“Our RISC-V processor is a MIPS-like processor, multithreaded, that supports hardware virtualization and cache coherency,” said Wasson.  He asserts that such high-performance and security support is finding its place in such areas as ADAS and intra-vehicle networking, the combination of ADAS and infotainment; hence the Mobileye engagement.

In addition, Wasson reckons the increasing use of electronics in vehicles – whether electric or internal combustion engine – will give rise to an increasing need for over-the-air upgrades. “ECUs will need to be real-time capable and able to handle multiple environments,” he said.

The P8700, a 64-bit, superscalar out-of-order operation RISC-V processor, is due for release at the end of 1Q24, Wasson said. “It is available as a scalable multicore cache coherent network-on-chip (NoC). It is also available in multiple clusters. It boots Linux and will come with documentation for inclusion in an SoC and will be safety-certified as well,” he added.

The design targets TSMC’s 7nm manufacturing process initially although MIPS engineers are working to go beyond that, Wasson said. “We may also have a 16nm optimization as well.” Wasson said that at launch the P8700 will be one of the highest performing RISC-V processor cores available.

Pro and con?

As an open-source architecture RISC-V is available for use royalty-free and comes with support for instruction set extension and design implementation by all-comers. However, those implementors can still license out their specific implementations and charge for engineering support. This marks a major distinction from the Arm architecture which is proprietary, and rigorously controlled by the UK company.

But could open-ness create both a benefit and a hindrance to users of RISC-V? The customization enabled by RISC-V allows for easier optimization for performance, energy-efficiency and other parameters, but that in turn could produce a market fragmentation that inhibits ecosystem support, or makes support more expensive?

Wasson sees it differently. “RISC-V allows you take the best of both cases. You have basic compliance of debug, trace and standards out of the box. There is a standard that provides interoperability. But you can then tune cores – just as you do elsewhere – for performance or power or data movement.”

The AI elephant

The elephant inside the R&D lab of just about every technology company in 2024 is artificial intelligence. Is AI processing or acceleration part of the MIPS roadmap?

“We will address AI by making sure we have the best data-movement processor,” said Wasson, indicating that he sees a major market in supporting GPUs and AI accelerators in servers for the datacentre. “MIPS may offer inference in time but there is an ecosystem requirement [that needs to settle] and I will wait on that,” he added.

“The software perspective comes first, but addressing things in the ISA is always going to be superior. And engineers don’t want to deal with multiple ISAs,” said Wasson. One of the issues is that AI is still relatively immature in terms of development and has a power consumption problem, Wasson explained.

AI hardware has so far been optimized for generality and for performance, he asserts. “We need to do more processing without blowing up the power consumption. AI has not yet been designed with power budget as a first constraint,” said Wasson.” When it is designed like that, Wasson indicates that RISC-V is a compelling choice.

Competitive landscape

Another aspect of the open-source nature of RISC-V is it is much more competitive that a proprietary ISA ecosystem. There are already many companies offering processor cores and supporting fabless chip companies with implementations. In contrast Arm is, in most aspects, a monopoly supplier around its own ISA.

As part of that competition MIPS is recruiting and senior executives Drew Barbier and Brad Burgess have joined the MIPS leadership team. Both were previously with RISC-V pioneer SiFive. Barbier joins MIPS as vice president of products and Burgess as chief architect (see MIPS recruits former senior SiFive execs to boost RISC-V play).

“RISC-V is a very active space. And I expect more competitors to show up,” said Wasson. “I don’t see that as negative. You need competition to bring out the best in engineering. But if we have the right fundamentals it comes down to our ability to execute,” Wasson concluded.

Related links and articles:

News articles:

SiFive lays off 20 percent of staff, re-aligns business

MIPS to drive RISC-V market penetration and innovation

MIPS recruits former senior SiFive execs to boost RISC-V play

Codasip delivers first commercial CHERI processor using RISC-V

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