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CEO interview: Preparing for the on-chip feedback revolution

CEO interview: Preparing for the on-chip feedback revolution

Interviews |
By Peter Clarke



It requires a different way of thinking about chips, both in terms of their role within systems and their life cycle, and it shows how rapidly on-chip monitoring IP is changing from what was only recently a simple, binary protection mechanism.

Moortec is a licensor of embedded intellectual property (IP) for process, voltage and temperature (PVT) monitoring, targeting planar and FinFET CMOS processes on 40nm, 28nm, 16nm, 12nm and 7nm.

The company was formed by Crosher and colleagues in 2005 with the aim to do something significant in semiconductors. They had previously been working for Zarlink Semiconductor, one of the manifestations of what had been GEC-Plessey Semiconductors. Some 15 years later Moortec is still relatively small but has roughly doubled in head-count over the last three years to reach 55 people.

But back in 2005, staffed with just a few analog circuit designers, the company decided to bide its time and start off by doing design services. This had the advantage of providing a revenue stream immediately, allowing the company to avoid debt or taking on equity funding. However, that startup phase ended up lasting five years.

“We’ve been profitable from day one and grew the company organically. We were developing our own design flows and processes and through that gained insight into the IP business,” said Crosher. “And we realized that analog design was going to have an important role to play in advanced digital nodes.”

In 2010, while still conducting analog and communications designs for clients, Moortec started developing reusable IP, Crosher said. “We’d noticed that up until that point, monitoring technology had tended to be developed in-house,” said Crosher. This was an opportunity for Moortec to relieve clients of what was becoming non-differentiating activity and help them focus on the rest of the complexity of getting 65nm and 40nm chips designed.

Next: analog IP for digital engineers


Crosher added that up until that time most monitoring had been thermal, providing basic on-off protection, either of the system, or of the processor chip, or both. “But we also realised that monitoring for more advanced nodes could become more sophisticated and more specialized, giving us a market opportunity.”

Crosher said other analog IP licensors were not competing in this area. They could be general IP or specialized IP but either way tended to be focus on what could be thought of as functional IP, such as phase locked loop (PLL), or serializer-deserializer (SERDES) blocks. “We were analog circuit designers selling to digital design teams. We packaged the IP to make it easier for them to integrate into the digital domain,” explained Crosher.

As a result, Moortec found its niche and decided to focus on on-chip process, voltage and thermal monitoring. And Moore’s Law and the increasing digital chip complexity has provided plenty of work for the company. “Over the subsequent ten years the requirement has evolved,” said Crosher.

“To begin with it was a bit of a tick-box exercise for on/off or safe-mode operation. But it evolved to in-chip monitoring underpinning overall optimization schemes,” said Crosher. Most notably this included the use of temperature and voltage monitoring for use in dynamic voltage and frequency scaling (DVFS) schemes.

A next step is multiple points of monitoring as an essential part of the functionality. “We are at 7nm and 5nm and heading down to 3nm and at this point I think of the chips as being like a Formula One car. Without sensors, a Formula one car would explode in short order.”

Moortec recently announced its distributed sensor subsystem aimed at TSMC’s 5nm  manufacturing process and that specifically supports this richer, fine-grained sensing (see Moortec recasts in-chip thermal sensor for TSMC N5 process).

Being able to monitor a chip and choke back performance brings other benefits, particularly for multiprocessor chips, Crosher added.

It allows wider process variability to be tolerated in manufacturing and therefore better yields and lower costs per chip. It can allow supply voltage reduction and improve tolerance to voltage spikes and IR-drops. Thermal monitoring allows greater gate densities than would otherwise be possible. By monitoring for hot spots and redirecting processing Moortec’s IP can reduce thermal stress and risks of electromigration of metals and increase reliability. It can be used for wear-levelling across multicore processors.

Next: Beyond PVT


So, is PVT monitoring also applicable to analog circuits and could this be an area of expansion for Moortec?

“We have looked at analog and mixed-signal at 40nm. There is a customer base there, but it is more nuanced in terms of what they are trying to achieve. We are mainly focused on advanced digital nodes where there is plenty of work,” said Crosher.

In terms of the company’s evolution Crosher states that between 2010 and 2017 it was a case of gradually gaining traction. “Doors were open and licensing was possible. But at 7nm/5nm PVT monitoring has become acutely important, if not essential.”

In July 2016 Moortec announced it had received an undisclosed of investment from Altitude Partners, a regional private equity fund. The money was to help grow the business and help with silicon validation of IP at more advanced nodes, Crosher said.

Crosher continued: “Now we’re going beyond PVT. There’s a revolution within the industry.” Crosher said that monitoring technology now has the opportunity to provide information at every stage of a chip’s life – on the wafer, in packaging and testing and in mission mode. “We can see opportunities in all phases, including predicting the chip’s end of life, and preventing operational failure.”

There are both semiconductor analytics and product analytics, he said. “Understanding how the chip is made means monitoring can allow optimization of individual chips to compensate for variation in the manufacturing process. It also means you can constrain the behaviour of the chip in the field to avoid compromising the chip. It also means you can allow design rules to be more relaxed than they otherwise would be.”

Next: Other processes


And these opportunities are certainly present with multi-cored processors and are, perhaps, even greater within artificial intelligence and machine learning accelerators. In short on-chip monitoring is becoming part of the essential feedback mechanism within dynamic behavioural systems made in silicon.

Does that mean there is scope for a greater digital element in what Moortec is providing in the form of IP, even providing on-chip analytics and machine learning?

Crosher responded: “The use of AI in our sector is probably a few steps away. But it is true that we are producing data and the users want useful information or calls to action. Data telemetry from the chip needs to be presented in a compressed and more meaningful way.”

Does Moortec support other foundries apart from TSMC and what about fully-depleted silicon-on-insulator (FDSOI) processes?

“In our history we have also supported SMIC, UMC and Globalfoundries,” Crosher replied. “We recognise that TSMC is leading the market with a progressive customer base. For many years, TSMC has been pushing the most advanced technology nodes, which aligns with our strategy of seeking to be first to market with sensing solutions, delivering to tier-1s initially.”

Moving on to FDSOI he said: “FDSOI is an interesting technology, with in-chip monitoring solutions linking well with dynamic back-biasing schemes. We continually assess opportunities within this space.”

Next: Expansion plan


Crosher takes an optimistic stance on the Covid-19 pandemic. “During lockdown there has been increased demand for consumer devices. The AI market is not slowing down. There has been a slowdown in industrial and automotive markets but that means we could be due a market bounce back. In any case products in these areas are on two- or three-year development cycles.

Crosher’s take is that, barring a significant second wave, the pandemic will have a six- to 12-month impact on global GDP. “We are very lucky because we have the ability to work from home and we work in the semiconductor industry, which is so dynamic. We’ll be able to weather this.”

So what about the future for Moortec?

“We wanted to do something special and meaningful. We feel we have that now. So, we’re looking to grow rapidly. We have a plan to get to 170 people in the next few years. And we will look at all options to accelerate that,” Crosher said.

The UK has a number of IP companies beside ARM and Imagination Technologies Ltd. Smaller, more specialist IP licensors include such firms as: Agile Analog, SureCore, UltraSoC and there is Imperas in the area of high-speed digital simulation. Would it create value, or a degree of protection against acquisition, for some or all of these small private UK companies to unite to form a larger company?

“There are many IP players in the UK and that is due to the quality of the innovative talent here. But we [Moortec] are holding our position. You have to be careful about retaining focus. But certainly collaborations can be very interesting,” said Crosher.

Crosher concluded: “We talked earlier about chip life-cycle assessment with the ability to predict end of life and prevent failure in operation as part of the information revolution. That will take specialist players in monitoring, analysis and other areas, but collaboration can address that opportunity.”

Related links and articles:

www.moortec.com

News articles:

Moortec recasts in-chip thermal sensor for TSMC N5 process

Opinion: China has had its way with Imagination

Agile Analog, UltraSoC team on cybersecurity

UltraSoC, Imperas partner up

Moortec, UltraSoC team up on DVFS process monitors

SureCore moves towards design services

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