As Black becomes CEO, Karel Masařík, the company’s founder and previously CEO/CTO, moves on to become Codasip’s president and responsible for advanced research and innovation. This will include such topics as graphics, AI and security, Black said.
Black has been with Codasip since March 2021 as executive chairman, during which time he has been building up its C-level suite of executives including the appointment of Rupert Baines as chief marketing officer, Brett Cline as chief revenue officer and Simon Bewick, as vice president of the UK R&D center.
Of his appointment as CEO Black said: “It was the plan from the beginning. Karel has done a fantastic job founding and scaling the company. He felt it was time to hand over.” Following Black’s transition to CEO, the company plans to appoint a non-executive chairman.
Codasip already employs just over 100 people at offices in Brno in the Czech Republic, Munich, Germany, and Sophia Antipolis, France, but with plans to employ another 100-plus engineers in the UK (see Codasip looks to hire 100 RISC-V engineers in Bristol, Cambridge) is the center of gravity of the company moving?
“The HQ will remain in Munich. The European Union is incredibly supportive of innovation but the UK is a fantastic place to find engineers with processor design skills,” said Black. “As well as Cambridge and Bristol we will probably open another office somewhere in the St Albans, Kings Langley area,’ Black said. Kings Langley is home to graphics processor IP licensor Imagination Technologies Ltd. a former employer from which Black resigned in April 2020 (see Imagination’s senior executives quit over potential Chinese coup).
With aggressive expansion plans for Codasip it would appear that Black is leading a team in a hurry. Is there a race on to establish critical mass as a leading supplier of RISC-V processors?
Next: Race to the top
“Yes, in the sense that if you are not already in RISC-V and have not been in it for a while then it is too late. I would have started my own company if I thought it was viable,” said Black. “There is a race to critical mass; put the gas pedal to the floor, but it is more than that. It is not just about RISC-V as the alternative,” said Black. He said that Codasip’s great strength is that it owns efficient hardware-software co-design technology; the subject of Masařík’s PhD thesis back in 2004.
“What attracted me to Codasip is the design tool ‘Studio’ and the processor description language CodAL. This gives the ability to automate processor description in response to software.”
Black then offered to step back and try and describe the opportunities brought about by the end of Moore’s law and Dennard scaling.
As transistor power consumption is proportional to capacitance, frequency and the square of the voltage, Robert Dennard proposed in 1974 that it should be possible to increase performance with scaling by operating at reduced voltages, less capacitance and higher frequencies.
That remained true until leakage current and threshold voltage started to become significant barriers and established a baseline of power per transistor. This created a power wall that has limited processor clock frequencies to a maximum of about 5GHz for more than a decade.
“The traditional general purpose processor mapped forward does not have [improving] performance, and remember a 5nm processor is a $500 million chip,” said Black referencing the potential development cost of a processor at the leading edge. “Hence the move to heterogeneous design and domain-specific design but there is still a problem with scaling. There’s basically three ways to fix it.”
Next: The three ways
The first way, said Black, is to move processors from electrons to photons. “There are some interesting startups out there doing that, but it is probably more than a decade away.”
The second way, Black said, is to change the materials. “There is some of that going on already. Carbon nanotubes might be the way. TSMC may include some of that in their 2nm process.”
The third way is hardware-software co-development, Black concluded. “The ability to profile the ISA [instruction set architecture] and the processor micro-architecture and tune them. That was exactly Karel’s vision.”
All therefore seems set fair for Codasip but startups need money. According to the readily available reports Codasip has only raised about US$15 million in total including a Series A round in December 2018 worth US$10 million. The Series A round brought in venture capital from Paris-based Ventech, Shenzhen Capital Group and Berlin-based Paua Ventures Verwaltungs GmbH plus Western Digital as a strategic investor.
Even though Codasip is a ‘soft’ company: with a ‘burn rate’ dictated by 100 going to 200 and more staff, what’s left of $10 million is not enough money to sustain a race for RISC-V supremacy.
“There have been investments in the company that we have not announced,” said Black. This makes sense as the progress in adding experienced senior management in 2021 could well have been stimulated by the injection of equity capital.
“And we have got significant revenue: and we are talking about IP product revenue not revenue from design services.” Reinforcing the sense of a company in command of its own destiny Black, with help from CMO Rupert Baines, then revealed an eye-catching statistic. “Two billion chips have shipped with Codasip RISC-V IP on board.”
At just 1 cent royalty per chip that represents a potential $20 million of revenue. If the royalty is higher, well the mathematics is obvious.
Next: Chiplet options
For our last we question we asked Black how he felt a move towards chiplet-style assembly of multi-die components would impact the IP cores market. In some senses chiplets can be seen as alternative to IP cores but one where the IP provider has to bear up-front cost for silicon production. “It is a natural extension of the IP delivery method. Some customers are already asking us for it,” said Black.
If so IP companies may become significantly less “soft” in the future and need more resources to pay for chiplet manufacture and the drop-off of bare die to advance packaging stations. But this would be reflected in pricing and allowing the chiplet vendor to keep more of the value they create.
Black concluded: “Strategically, Codasip is in a strong place – the right market with astonishing technology and a world class engineering team, but it’s a well-kept secret. RISC-V opens incredible opportunities for customized processors and IP using Codasip’s Studio EDA tool and CodAL processor description language, arguably the easiest way to develop such high-quality, differentiated products.”
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