CEVA aims at hardwired audio processors with TeakLite 4
The core was specifically designed to address the increasingly complex requirements of voice pre-processing and audio post-processing algorithms as well as multi-channel audio codecs, for smartphones, mobile computing and digital home devices. With under 100,000 gates, the low end of the platform is small enough to put alongside a digital-to-analog converter (DAC) to provide a low cost integrated audio subsystem.
TeakLite-4 uses up to 25% less die area and requires up to 30% less power than the previous generationTeakLite-III DSP for decoding MP3 with Dolby Mobile 3+ post-processing. This has come from optimising the instiruction set for audio, reducing the number of gates required in the execution unit by combining stages. CEVA has also developed a new power management unit with finer grained power gating to switch off units that are not being used on a cuycle by cycle basis.
Additional performance is required over the configurable hardwire audio processors and this is driving the move to a programmable core, says Eran Briman, vice president of marketing at CEVA. To deliver better voice intelligibility in noisy environments for example, advanced pre-processing technologies reduce the background noise and improve voice clarity, requiring support for computational-intensive algorithms. Likewise, the transition to wideband voice codecs for voice-over-LTE (VoLTE) and voice-over-IP (VoIP) applications requires significantly more DSP horsepower than traditional narrowband voice codecs used today. In mobile and home entertainment devices, audio post-processing creates a vastly-improved consumer experience, delivering virtual surround sound, speaker correction, bass expansion effects, and more. The processing required to deliver this level of performance is significantly more complex than what can be efficiently achieved with 16-bit and 24-bit DSPs, driving the need for 32bit audio processingt.
”In architecting the CEVA-TeakLite-4, we built upon the vast knowledge and experience gained in the last five years from our first generation 32bit audio processors to significantly improve the performance and power efficiency of our new architecture," said Briman. "As a result, the CEVA-TeakLite-4 architecture can address the specific requirements of any advanced audio and voice enabled SoC through a choice of scalable and flexible DSPs, which share a common instruction set architecture, software ecosystem and tool set. Furthermore, the integration of our second generation smart power management technology, PSU 2.0, enables the TeakLite-4 architecture to deliver the lowest power consumption package possible, for each specific application.”
TeakLite-4 architecture is initially available as a series of four compatible DSP cores, offering designers a range of application-specific cost/performance alternatives to meet their application requirements. The TL410 and TL411 DSPs offer single and dual 32×32 bit multipliers, respectively, targeting voice and audio CODECS and hubs, while the TL420 and TL421 DSPs offer additional fully cached memory subsystems and AXI system interfaces, targeting Application Processors and home audio SoCs. Courtesy of a variable 10 stage pipeline, the architecture scales from an area-optimized implementation of less than 100K gates and ultra-low power consumption, up to a 1.5GHz implementation at 28nm for high-end SoCs. All the TeakLite-4 DSPs leverage CEVA’s second generation Power Scaling Unit (PSU 2.0) which dynamically supports clock and voltage scaling with finer granularity within the processor, memories, buses and system resources.
TeakLite-4 is fully compatible with every previous generation of the CEVA-TeakLite, ensuring that the full portfolio of voice and audio codecs optimized for the CEVA-TeakLite architecture runs on the CEVA-TeakLite-4 with improved efficiency. By taking advantage of a unified development infrastructure composed of code-compatible cores, a set of optimized software libraries and a single tool chain, customers can significantly reduce software development costs while leveraging their software investment in future products.
The CEVA-TeakLite-4 DSPs are supported by CEVA-Toolbox software development environment, enabling the entire architecture to be programmed in C-level. An integrated simulator provides accurate and efficient verification of the entire system including the memory sub-systems. In addition, CEVA-Toolbox includes libraries, a graphical debugger, and a complete optimization tool chain named CEVA Application Optimizer. The Application Optimizer enables automatic and manual optimization applied in the C source code.
The first members of the CEVA-TeakLite-4 DSP family will be generally available for licensing in Q2 and Q3 of this year and in products in 2013.
For more information, visit www.ceva-dsp.com/CEVA-TeakLite-4.html.
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