CEVA claims “most efficient processor architecture for baseband”

CEVA claims “most efficient processor architecture for baseband”

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By eeNews Europe

The IP vendor says that the architecture,”brings an innovative holistic approach to modem architecture, orchestrating DSPs, coprocessors, hardware accelerators, memories and system interfaces” – the first member of the CEVA-X family is the CEVA-X4 multi-RAT multi-carrier PHY control processor targeting 2G/3G/4G/5G modems.

With a scalable VLIW/SIMD architecture, up to 128-bit SIMD, a variable length pipeline and support for both fixed- and floating-point operations, the new CEVA-X delivers 2X more DSP throughput while consuming 50% less power than the previous generation CEVA-X. The architecture also includes a dedicated 32-bit zero-latency Instruction Set Architecture (ISA), 32-bit hardware division and multiplication, dynamic branch prediction and ultra-fast context switching for the efficient control processing required in modern baseband designs.

The CEVA-X4 was designed to solve three critical challenges in next generation modem designs:

-Efficient control processing: for multi-carrier aggregation there is a significant increase in L1 PHY control processing. For example, next-generation Rel-13 LTE Advanced Pro modems are required to deal with up to 5 carrier components in parallel and handle multiple PHY control tasks on multiple carriers, in tandem.

– Powerful DSP processing: a considerable boost in DSP performance is required to support a heavy LTE workload including per-channel measurement, calibration and decoding, as well as legacy RAT.

– Advanced system control: complex system scheduling and data traffic management is essential to deal with the many accelerators, DSPs and coprocessors in the system, within a low latency constraint.

To overcome these challenges, the CEVA-X4 incorporates a set of baseband-optimised features and functions in a highly efficient manner. This 128-bit wide VLIW/SIMD processor features 8 MAC units in 4 identical Scalar Processing Units (SPUs) and a 10-stage pipeline, capable of running at 1.5 GHz in 16nm and achieves 16 Giga Operations Per Second (GOPS). The processor’s efficient control features include an integer pipeline, a complete 32-bit RISC ISA including hardware division and multiplication, and a Branch Target Buffer (BTB), achieving CoreMark / MHz score of 4.0, 60% better (per thread) compared to the most established in-house DSP used in smartphones today.

For system control, the CEVA-X4 brings a holistic approach to modem design, using the CEVA-Connect technology to orchestrate the entire PHY system, comprising of DSPs, coprocessors, accelerators, memories and system interfaces. It is equipped with dedicated hardware coprocessor interfaces and an automated data and control traffic management mechanism that eliminates any software intervention. Its memory subsystem supports an advanced non-blocking 2-way or 4-way caches with hardware and software pre-fetch capabilities.


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