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CEVA teams with ARM on vector floating-point DSP core for wireless infrastructure

CEVA teams with ARM on vector floating-point DSP core for wireless infrastructure

Technology News |
By eeNews Europe



The CEVA-XC4500 includes a baseband-dedicated instruction set architecture (ISA), IEEE-compliant floating point support on full vector elements delivering up to 40 GFLOPs performance, comprehensive multi-core support, a fully cached architecture and hardware managed coherency. The core uses as little as 100mW for LTE 2×2 Pico-Cell baseband processing.
The core is fully cacheable with an advanced data cache that includes hardware cache coherency via ARM’s AMBA 4 ACE, and includes an advanced system interconnect using a mix of ARM AMBA 4 compliant buses and fast interconnect (FIC) buses to other system blocks. It also comes with a set of LTE eNodeB libraries.
“The CEVA-XC4500 DSP is a game-changer for wireless infrastructure applications, combining powerful fixed- and floating-point vector processing together with the industry’s most advanced multi-core feature set in a flexible, scalable platform," said Eran Briman, vice president of marketing at CEVA. "The DSP was designed to enable the creation of infrastructure SoCs that combine a software-based architecture together with optimized hardware accelerators, realizing maximum performance and power efficiency for any wireless infrastructure use case. We collaborated closely with ARM to ensure comprehensive support for their latest industry-standard interconnect and coherency protocols, enabling our mutual customers leverage the inherent advantages of designing ARM + CEVA-XC multi-core SoCs.”
Several important emerging technologies such as heterogeneous cellular networks (HetNet) and cloud RAN (C-RAN) require more powerful, higher performance processing solutions to deliver on their promise. The CEVA-XC4500 DSP runs at up to 1.3GHz on a 28nm process and the vector DSP engine supports Fixed Point and Floating Point (IEEE compliant) ISA on full vectors. This enables software-defined architecture with a mix of optimized hardware engines for DSP offloading and a range of tightly coupled acceleration blocks (TCE – Tightly Coupled Extensions) are available. Automated data traffic management offers fully parallel hardware acceleration management with no DSP intervention while dynamic scheduling enables symmetric system design with runtime task allocation based on system load
The core is able to address any wireless infrastructure use case, including baseband: from small cells (Pico, Metro) to macro base stations and cloud RAN (C-RAN); Wi-Fi offloading; wireless backhaul, and; remote radio heads.
“We are pleased to collaborate with CEVA to meet the needs of businesses and consumers worldwide as the relentless growth of data consumption continues to challenge wireless networks,” said Charlene Marini, vice president, Marketing, Embedded Segment at ARM. “The next generation of wireless infrastructure can be enabled by heterogeneous multi-core processors that combine ARM’s high-performance, low-power processors, connected by high-performance cache-coherent interconnects with CEVA DSPs and hardware accelerators.”
The CEVA-XC4500 DSP architecture is supported by the CEVA-Toolbox software development environment, incorporating Vec-C compiler technology for advanced vector processors and enabling the entire architecture to be programmed in C. The Integrated simulator and profiler provide accurate modeling of the entire system including: caches, DMA controllers, interfaces, tightly coupled extensions, and more. In addition, CEVA-Toolbox includes a new set of LTE/LTE-Advanced eNodeB libraries introduced for the CEVA-XC4500 for the first time, which complements the existing comprehensive library suite for Wi-Fi, TD-SCDMA, WCDMA and HSPA+.
www.ceva-dsp.com/CEVA-XC4500

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