CEVA unveils core for DSP control processing in 5G
The CEVA-X2 has been designed to tackle the PHY control complexity increase of LTE-Advanced Pro which includes Rel.13 multi-carrier and multi-standard handsets. Where the PHY Datapath tasks such as per-channel measurement and decoding are not required to run on the DSP, CEVA-X2 is claimed to offer a 30%-65% better die size efficiency and 10%-25% better power efficiency compared to CEVA-X4 DSP. The CEVA-X2 is also appropriate to run both the PHY and MAC for a range of other communication standards, including IEEE 802.15.4g, ZigBee, Thread and power line communications (PLC), combining power efficiency with minimal die area for such use cases.
Features of the IP include;
VLIW/SIMD architecture
10 stage pipeline
128 bit memory bandwidth
4.0 Coremark/MHz
Four-MAC 16×16 per cycle
64-SIMD fixed-point operations
Up to two IEEE single-precision floating-point operations
1.5GHz operating frequency in 16nm finFET
Instruction and data caches
Branch target buffer
CEVA-Connect Technology to schedule control and data planes of hardware accelerators
Controller features comprise;
Four scalar operations per cycle
Zero latency ISA
Static branch prediction
Optional dynamic branch prediction
32-bit HW division and multiplication
Ultra-fast context switch
Supervisor and User modes
Semaphores
DSP features include;
Two SPU (Scalar Processing Unit)
Four 16×16 MAC per cycle
Two 32×32 MAC per cycle
64-bit SIMD processing
8/16/32/64 bit data type support
8/16/32/64 bit ALU operations
Four 16-bit operations per cycle
Two 32-bit operations per cycle
Two 64-bit operations per cycle
Optional single-precision IEEE floating point in each SPU
Loop buffer
More on the IP’s web page.
Ceva; www.ceva-dsp.com
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