The China Chiplet Industry Alliance has released the ‘Chiplet Interconnection Interface Standard’ known as ACC1.0, according to the Financial Association Press.
The standard defines a high-speed serial port and is focused on optimization based on the domestic packaging and substrate supply chain, with cost and commercial practicality as a key consideration, the report said. The standard was developed by the Cross Information Core Technology Research Institute working with the China Chiplet Industry Alliance, which includes domestic system, IP, and packaging manufacturers.
The use of multi-die components rather than monolithic integration is a trend in semiconductors that is gradually moving down from the high-value processor plus memory combinations to ASICs. It allows each component subsystems to be manufactured in the most appropriate and cost-effective manufacturing process before being brought together using an active or passive silicon interposer.
This could allow China’s trailing edge manufacturing capability to continue to contribute to relatively advanced IoT ASICs although the use of leading-edge processes is still required for leading-edge logic circuits such as software programmable processors and AI/ML circuits.
The report of the development provided no details of the ACC standard. It did say that China expects the adoption of chiplet technology to proceed from upstream IP development through EDA and design to mid-stream manufacturing and then down to packaging and testing.
Huatian Technology’s chiplet series technology has achieved mass production, which is mainly used in 5G communications, medical care, Internet of Things and other fields. Kunshan Tongxingda offers chiplet related technologies such as gold bumping and full-process packaging and testing.
Outside China a number of leading companies have formed the Universal Chiplet Interconnect Express organization. These include: AMD, Arm, ASE, Google, Intel, Meta, Microsoft, Qualcomm, Samsung and TSMC.