China researchers report 256 core, chiplet-based processor
The China Academy of Sciences has reported on a chiplet-based architecture of “Big Chip” as a means of exploring the challenges and options for scaling processor performance.
The research team reports on a 16-chiplet based 256 core RISC-V processor system named the Zheijiang Big Chip. The chiplets are made using a 22nm CMOS manufacturing process.
Each chiplet, contains 16 RISC-V processors that are connected via a network-on-chip (NOC), and is fully symmetrically interconnected to enable communication among multiple chiplets. The Big Chip architecture has the potential to scale up to 100 chiplets, the authors claim in a the Elsevier journal Fundamental Research.
To connect multiple chiplets a die-to-die interface is employed with an interconnect time-multiplexing technique that supports a unified memory system as any core on any chiplet can access memory across the entire system. The time-multiplexing minimizes the area overhead of I/O bumps and reduces interposer wiring complexity.
In the paper the authors maker reference to Cerebras wafer-scale 2D chips WS1 and WS2 and to chiplet based high-performance processor developments from AMD and Nvidia.
Conclusions drawn by the authors are that for future development support for near-memory computing and optical-electronic chiplet communications will be important research directions.
Related links and articles:
The Big Chip: Challenge, Model and Architecture
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