Chip designer brings test back to Europe
European mixed signal chip designer ICsense has installed a leading edge tester in Belgium to reduce the supply chain risk.
“We wanted to bring this part of the supply chain back to Europe, not in the Far East and that is also to protect us as we see the slots we get are getting harder to get at the bigger test houses,” Bram De Muer, co-founder and CEO of ICsense told eeNews Europe.
“Especially the case with the engineers that do the test development as their time is very limited and that can take six months which is a critical part of mass production. With the tester in house it’s just over a month and we are trying to make that shorter. The communications loop is really short and for our customers there is a single point of contact.”
The ASIC house has installed Advantest’s V93000 Smart Scale system at its headquarters in Leuven as part of a move to production test of chips.
“There are only a few IC design houses in the world and, typically, these companies design custom chips internally but do not necessarily have the in-house resources to execute on the steps that follow,” said De Muer. “It takes several years to develop a custom IC. The team that develops the chip knows it inside out, making it vitally important that the test development team is also in-house to bring the product to mass production successfully.”
“We are mostly analogue focussed for power management, PMIC, battery management, HV, providing design services and complex ASICs for medical, automotive and high reliability applications,” he said.
“We did a whole exercise on testers from Teradyne, Credence, to see what was compatible now and in the future,” he said. “We may be a bit early with Advantest but we see our big partners such as ASE moving to the 93K. We chose the 93K because it is versatile with Java rather than C which is easier than C to programme and debug, as one day it’s a sensor ASIC to test, the next a PMIC.”
This is important for the range of different designs, foundries and process technologies that the company uses.
“We evolved to be an ASIC supplier with test houses and IDMs to bring chips in mass volume to the market, and that’s the next step. We wanted to take that part of the supply chain in house in particular the test programme development as you gain insights into the design and can optimise the production test time. It allows us to do the lower volume tests in house and we team with the test houses for mass production but we do the yield control, that’s a big difference,” he said.
“Since 2017 we have been part of the sensor systems with Invensense and Micronas, and 50 percent of the business is for TDK companies and 50 for others,” he said.
The move to test is even more important with the push to smaller geometry designs from a range of foundries using a process-independent design flow. “We are leaving 0.35 micron to 180nm, and TSMC are pushing us to go to 130m BCD and 90nm. For sensing 110nm is the sweet spot
“On the design side from day one we set up a methodology with Cadence and Synopsys tools with a framework around it to enable it to be process technology independent and that same methodology we use for test as well. What we are trying to do is a lot more structured with reuse in the test programmes eg for a bandgap, a sensor readout or an LDO. We develop these programme to be parameterisable for production test.”
The company aims to build up a significant test expertise in Europe, as test development can be as much as one third of the cost of a mixed signal chip.
“My biggest challenge is people, it’s a huge challenge,” said De Muer. “We get them from everywhere. Being part of TDK helps, it’s a good brand. Apple is building a big design centre in Munich so they will be grabbing people there, Invensense did the same thing in Italy. The amount of people who graduate in analogue electronics is going down rapidly and that will be a huge issue, and we work with the University of Leuven and sponsor research at the University of Delft [in the Netherlands] which helps.”
“Test development engineers are even harder to find than analogue designers – with the 93K you can build your test programmes in a virtual framework and you only need someone at the tester occasionally for programme. We are training engineers ourselves to grow the team and we want that team to be at least 10.
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