Chip-level layout editor speeds final physical design steps
Chip finishing is one of the last physical design steps before manufacturing and generally requires engineers to merge large design files, run design rule checks (DRC), and make final corrections, all while under enormous schedule pressures. Currently, they most likely use layout tools or viewers that have been optimized for other tasks and have limited performance or minimal editing capabilities. By contrast, SpringSoft’s Blitz software is specifically optimized for speed and user productivity during the chip finishing part of the design cycle, in keeping with the company’s focus on providing specialized solutions that address key pain points in the chip development process.
It loads and exports GDSII data files 5 to 20 times faster than conventional layout tools, claims the EDA vendor, offering more robust layout editing capabilities than most high-capacity layout viewers, and providing an extensive library of Tool Command Language (Tcl) extensions for automating data manipulation. Designers can perform cell, window or full-chip DRCs, and then find and fix violations without leaving the Laker Blitz environment. Layout editing and debug at the chip-level is further simplified with advanced features, such as net highlighting commands to trace critical nets.
Visit SpringSoft at www.springsoft.com/products/laker-custom-ic-design-solutions
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