UK chip design house Sondrel is warning of issues in chip packaging with lead times increasing from around 8 weeks to as much as 50 weeks or more.
Packaging houses were badly hit by cancellation of orders in the early days of the Covid-19 pandemic and had to lay off staff or even close down. As silicon production surges, they are struggling to cope with the boom in orders with existing capacity, pushing out delivery times.
- Driving leading edge chip design from Europe
- Sondrel tapes out its largest chip
- Sondrel looks for 100 engineers as it ramps 5nm designs
“The sequence of booking the stages in the supply chain has completely changed. Previously the design would be finished and then sent off to be made into wafers, which still takes around 12 weeks. At the same time, the details for the packaging would be sent to the packaging company so that was ready before the silicon,” said Alaa Alani, Sondrel’s Head of Packaging. “The new timeline means that the packaging design has to be finished and booked 20 or more weeks before the final silicon design to ensure that the silicon and packaging come together at the right time.”
Not being aware of this and planning accordingly could introduce a delay in the production of a chip by as much as 40 weeks. Sondrel offers a complete turnkey ASIC design and manufacturing service and so has spotted this as a growing problem in the supply chain.
One way to minimise the impact of the delays is to start the SoC package planning and design by assigning die bumps and assigning their x/y coordinates relative to the die corner. Moving this stage to much earlier in the supply chain sequence avoids a massive and costly delay.
The bump locations are determined for each of the macros and PHYs as specified by the IP vendors using the floor plan and the SoC partitions’ locations. For hard macros such as PCIe, HDMI and others, the bumps locations are specified by their relative offset from the macro corner whereas in soft macros (e.g., DDR), it is based on a certain pattern and a minimum pitch used in the bump assignment.
“Our reputation is based on mitigating the risk of a customer’s project by ensuring the quality of our design work and keeping our fingers on the pulse of every stage of the supply chain to identify and solve issues so that the chips are delivered on schedule,” said Graham Curren, founder and CEO at Sondrel.
- Sondrel semi-custom 4TOPS AI design
- Sondrel launches quad channel IP for ADAS ASICs
- Sondrel agrees to buy Imagination SoC design group
Other articles on eeNews Europe
- Synopsys boosts chip design with cloud platform
- Earth digital twin project launches
- Glass processors aim to boost edge AI
- Swiss deal to boost quantum computer design