Chip stacks take new tacks
The smartphone application processor was supposed to be the vehicle for TSVs, and Qualcomm was going to be one of its drivers. Now Apple is out front with speculation its next A-series SoC will use TSMC’s wafer-level fan-out process in a 10nm chip in the works for the iPhone 7.
Whether the Apple rumor is true or not, Qualcomm confirmed it is no longer interested in 3D chip stacks with TSVs. The approach cost too much and takes too long to manufacture, said Michael Campbell, a vice president of engineering at Qualcomm in a talk at the Industry Strategy Symposium hosted by the SEMI trade group.
Instead, Campbell pointed to an emerging class of system-in-package technologies such as the device in the Apple Watch that merge multiple die and passive components. “It’s a question of cost and time-to-market…TSVs require a two-year-plus design cycle while these micro packages take 6-12 weeks,” he said.
Heat is a chief problem for TSVs, said Babak Sabi, director of assembly and test development technology at Intel in an ISS talk. “No one has true stacking of memory on logic and unless someone comes up with a thermal solution for the logic die I don’t think anyone’s going to use it,” he said.
E. Jan Vardaman, president of TechSearch International, a veteran analyst of chip packaging technology, agreed.
“Years ago Qualcomm and Samsung did a lot of work on TSVs and had demos, but the problem was you can’t get rid of the heat…hot spots on the logic die would heat memory die past their rated temperature specs…and there’s no air flow or room for cooling systems [in the tiny chip stacks]—that was the first technical show stopper,” said Vardaman.
The good news is the industry is awash in alternative ways to package chips including stacks of memory chips using TSVs. “I think the idea of TSVs in logic is waning, but not TSVs in memory,” said Ron Huemoeller, corporate vice president for R&D at Amkor Technology which has a variety of options including its own versions of fan-out packages like those of TSMC.
The new packaging options are among the best hopes for driving gains in chip performance, size and cost at a time when Moore’s Law is slowing down.
“The semiconductor curve isn’t quite cutting it anymore, its good but it isn’t what it used to be…but with the miniaturization of packages we can get back to the curve,” said Campbell. “We’ve always been about the semiconductor fab and the extreme value it provides, now we have to bring in other partners, the assembly and board makers,” he said.
Vendors are offering more than half a dozen versions of wafer-level fan-out packages, a technology set to grow by 87% this year, Vardaman projected.
Infineon was an early pioneer of the approach for baseband chips with its eWLB technology (above), now owned by Intel as part of its acquisition of Infineon’s wireless group. NXP is using similar technology in modules for the Internet of Things from the newly acquired Freescale. Amkor, ASE, Marvell and others have similar capabilities.
Given the Apple rumors, “one can safely assume Samsung would be working on something similar” for Galaxy smartphones that could emerge as early as February, said Vardaman.
Most fan-out packages use a mold compound as a substrate or redistribution layer to create a package slightly larger than the die itself where solder balls are placed. TSMC takes a slightly different approach to Infineon’s original eWLB by using copper posts.
Typical fan-out designs that use a die-up approach, but Amkor is ramping up a variant it calls Swift built with a die-down orientation. The package could be used to marry a wide variety of memory and logic parts including applications processors and RF devices. Because all work is done in house, it is one of the lowest cost chip stacks Amkor offers and will be in production late this year, said Huemoeller.
Amkor is developing Swift as an advanced fan-out package, also good for SiP. (Image: Amkor)
Qualcomm called for work in several areas to advance system-in-packages. (Image: Qualcomm)
The system-in-package concept is less clearly defined but possibly even hotter than fan-out. Essentially, SiPs put multiple die and passives in a single package, typically targeting a broad system function.
The Apple Watch processor is the poster child for SiP today, described by Campbell as “the most complex module in the industry…system-in-package integration allows you to pick the best process node for every function, re-use system software and achieve smaller systems form factors,” he said.
The miniaturization inside any sports watch is a good example of the goal, Campbell said. Such a package could cram the key components of a future smartphone into the size of a quarter and “change the industry,” enabling a new class of IoT modules, he said.
Some technology barriers lay ahead. For example, Campbell called for an RF-to-baseband interface suitable for a chip stack, passives such as resistors better suited to SiPs and new test procedures and probes geared for the new level of miniaturization.
“The mega data coming from these IoT modules will drive new industries,” he added.
At the high end, 2.5-D packages are gaining traction in networking and graphics companies such as Cisco Systems, Juniper Networks, AMD and Nvidia. Prices for the packaging came down as much as 40% in 2013, driving broader adoption in generally high performance, moderate volume products such as processors and ASICs.
Among alternatives, Amkor is working on a multi-die package it calls Slim. It does not require TSVs or thinned wafers, using instead a simpler back-end approach available at any 300mm wafer fab with copper.
Intel has its own lower-cost approach to 2.5-D using a small silicon bridge linking die rather than a full interposer. The so-called Embedded Multi-Die Interconnect Bridge (EMIB) doesn’t carry the power and latency penalties of typical 2.5-D processes.
“There are many different packages to meet the requirements of different market segments,” said Intel’s Sabi.
Overall, getting to “smaller vias is the biggest roadblock…we have laser drilled vias now at 20-60 microns and spaces are 10-20 microns… But only so much can be done with laser drilled vias, we need photo image-able dielectrics,” he said.
Intel hopes to push the boundaries, collaborating on the development of new packaging systems and materials. For example, it worked with a laser vendor to make a system capable of drilling 15 micron vias needed for some of its EMIB packages.
About the author:
Rick Merritt is Silicon Valley Bureau Chief at EE Times