Chip-to-chip high bandwidth interconnect from OpenFive

Chip-to-chip high bandwidth interconnect from OpenFive

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By Peter Clarke

OpenFive, which owns customizable IP for artificial intelligence, edge computing high-performance computing and networking, was announced in August 2020 (see SiFive design unit partners with ARM, others). AnalogX was founded in 2017.

The two companies have announced a sub-system for chip-to-chip interfaces that can be optimized for bandwidth requirements from AI, HPC, storage, aerospace and 5G basestations.

The sub-system is based on Interlaken controller IP from OpenFive supporting from 1 to 48 SerDes lanes with up to 112Gbit/s rates. The AnalogX die-to-die SerDes offers sub-picojoule per bit energy consumption and multi-terabit per millimeter area efficiency.

AnalogX XSR/VSR chip-to-chip SerDes offers a1.5pJ/bit solution while providing approximately one terabit-per-mm area efficiency. AnalogX XSR/VSR configurations support up to 20 parallel lanes and AnalogX multi-protocol SerDes offers 2.5pJ/bit energy efficiency for PCIe Gen 5 connectivity while offering compatibility with CCIX, CXL, and other standard protocols. AnalogX IPs are currently available across multiple foundries and 22nm, 16nm, 12nm, 7nm, and 6 nm technology nodes.

Related links and articles:

News articles:

SiFive design unit partners with ARM, others

SiFive creates global network of RISC-V startups

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