Chip trio speeds data exchange within ADAS

Chip trio speeds data exchange within ADAS

Partners |
By Christoph Hammerschmidt

In Advanced Driver Assistant Systems (ADAS), the demand for high computing power meets the necessity for high functional safety. These tasks typically are shared by two instances: A number crunching device (e.g. Nvidia) and a “safety guard”, typically implemented by a processor of Infineon’s Aurix class. Now Xylon together with Xilinx and Infineon have developed a piece of IP that enables much faster data exchange between the safety guard and Xilinx-based number cruncher platforms. This IP, Xylon’s logiHSSL, speeds the data connection between Infineon’s Aurix TC2xx and TC3xx microcontrollers and SoC, MPSoC and FPGA devices from Xilinx. Data is exchanged via Infineon’s High Speed Serial Link (HSSL) – with baud rates of up to 320 Mbaud and an effective bandwidth of up to 84%

HSSL is a proprietary Infineon interface that requires only five pins – two LVDS with two pins each and one clk pin. So far, it has been used for data exchange between Aurix microcontrollers and customer ASICs to extend computing power or functionality. With the new IP core, developers can combine Aurix’s high security level with the wide functional scope of Xilinx products. PCB-connected devices can exchange data and access each other via HSSL – including externally connected resources.

Infineon’s Aurix processor is used in many safety-relevant applications, such as driver assistance systems and automated driving. The improved data exchange capabilities between these processors and other SoCs and FPGAs within a system result in extended options for customers, especially in new applications with high demands on both computing power and security. In addition to automotive applications, this also includes industrial automation.

Xilinx SoCs and FPGAs are used in ADAS and Automated Driving architectures for data compression, pre-processing and distribution, and as coprocessors. “Combining this with functional safety at ASIL D level, as enabled by the Aurix family, has led to a strong demand for an FPGA-based HSSL solution,” said Paul Zoratti, Director Automotive Solutions at Xilinx. “Xylon’s IP core allows customers to establish a reliable HSSL communication path between Xilinx and Infineon products with minimal development effort.

The partners offer a starter kit for development support. It includes an evaluation kit from Xilinx, an Aurix evaluation board from Infineon and an FMC board from Xylon. In addition, there is a reference design with the test software, evaluation licenses for logicBRICKS from Xylon, documentation and technical support. The new IP core and development kit will be available from March 2019.

More information here.

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