Chiplet standards group launches

Chiplet standards group launches

Technology News |
A range of developers of semiconductor, packaging and IP have teamed up with foundries and cloud service providers on a standard for chiplets. The Universal Chiplet Interconnect Express (UCIe) 1.0 specification provides a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing to enable end…
By Nick Flaherty

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A range of developers of semiconductor, packaging and IP have teamed up with foundries and cloud service providers on a standard for chiplets.

The Universal Chiplet Interconnect Express (UCIe) 1.0 specification provides a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing to enable end users to easily mix and match chiplet components.

UCIe is based around PCI Express (PCIe) and Compute Express Link (CXL) industry standards.

The group includes Advanced Semiconductor Engineering (ASE), AMD, ARM, Google Cloud, Intel, Meta (Facebook), Microsoft, Qualcomm, Samsung, and TSMC.

 

The group, which will be incorporated later this year, will address customer requests for more customizable package-level integration in the next generation specification. This will include defining the chiplet form factor, management, enhanced security, and other essential protocols

The Universal Chiplet Interconnect Express (UCIe) Specification is now available. This is a layered protocol where the physical layer is responsible for the electrical signaling, clocking, link training and sideband links.

The Die-to-Die adapter provides the link state management and parameter negotiation for the chiplets. It optionally guarantees reliable delivery of data through its cyclic redundancy check (CRC) and link level retry mechanism. When multiple protocols are supported, it defines the underlying arbitration mechanism.

A 256-byte FLIT (flow control unit) defines the underlying transfer mechanism when the adapter is responsible for reliable transfer. UCIe maps PCIe and CXL protocols natively as those are widely deployed at the board level across all segments of compute.

The usage models addressed are also comprehensive: data transfer using direct memory access, software discovery and error handling are addressed with PCIe/ CXL.io; the memory use cases are handled through CXL.Mem; and caching requirements for applications such as accelerators are addressed with CXL.cache.

UCIe 1.0 also defines two types of packaging. The standard package (2D) is used for cost-effective performance while the advanced packaging is used for power-efficient performance.

A “streaming protocol” can be used to map any other protocol, which will be part of the next generation specification.

www.UCIexpress.org

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