Chiplets drive new automated design tools at Leti

Chiplets drive new automated design tools at Leti

Technology News |
By Nick Flaherty

Cette publication existe aussi en Français

CEA-Leti has shown a scalable chiplet architecture for automotive and developed new automated tools for design exploration.

The move to software defined vehicles and zonal architectures is also driving the need for chiplets and new design tools at French research group Leti in Grenoble.

“Two years ago we started a feasibility study with a big automotive OEM to define and specify the high level architecture of E/E architectures and at that time there were only two solutions: a SDV based on a GPU and a discrete solution,” said Denis Dutoit, programme manager for advanced computing and chiplets at CEA-Leti.

This chiplet architecture was described at the Leti Innovation Day today.

“This architecture will require a new design methodology as the design space is so huge the traditional way of designing system is no longer valid,” he said.

“For the next generation of e/e the systems are grouped by physical location with central compute in a zonal architecture, but this has challenges with scalability. We have seen the gap between low end and high end is 100TOPS to 1000TOPS in compute and 100Gb/s to 1000Gb/s in memory bandwidth, and then there is the issue of cost.”

“We started with the definition of the low end car, starting with an IO chiplet. This is a monolithic die that is also able to handle minimal processing for low end applications as a fusion chip that can handle cameras and displays. For more performance we have defined a computing extension for this chiplet and this is software defined.”

“For ADAS, the amount of computing is so huge you need a specific accelerator so we also defined an ADAS chiplet to handle more cameras and more sensors. Now we want to scale to the high end for infotainment with a new IO chiplet and a new compute chiplet.”

This leads to nine systems options which need new tools to explore the design space. “Instead of designing nine SOC we have defined three chiplets for five architectures for each segment with four packaging options, two for standalone low cost platforms, I/O + Compute and quad ADAS.”

Leti previously developed virtual prototypes with its own simulator called  VPSim for benchmarking. This simulator has a good tradeoff between speed and accuracy but this is not good enough for the chiplets he says. “We are designing a new development flow with automated exploration of the design space so that from just the parameters with simulation, we can propose candidates and extract the key performance indicators (KPIs) and generate binaries to preform the benchmarks,” he said

This is the MCPAT simulator for multicore power and area simulation and also includes execution time of the application and cost of the solution.

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles