Chipmakers stand up to back Synopsys’ chip area gains

Chipmakers stand up to back Synopsys’ chip area gains

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By eeNews Europe

Elmos Semiconductor reports up to 10% reduction in gate count on mixed signal design: Kyocera Document Solutions also reports 10% smaller area. Synposys points to its new monotonic area optimisation engine as providing improvements in area and power while preserving timing results.

These names underpin Synopsys’ statement that multiple customers have achieved smaller area using the latest releases of its Design Compiler RTL synthesis solution, within the Synopsys Galaxy Design Platform. Aggressive area optimisation is critical for designers across a wide range of electronic applications to either reduce system costs or implement additional functionality without increasing die size. Innovations in the latest releases include advanced optimisations operating with and without physical information, which lower power and produce smaller, more routable designs without impacting timing.

Michihiro Okada, general manager of the Software 3 R&D Division, Corporate Software Development Division at Kyocera Document Solutions is quoted, "Design Compiler’s new monotonic area optimisation reduced design area by 10% for multiple designs while meeting timing requirements and lowering leakage power. This allowed my design team to implement additional functionality without an increase in die cost."

Similarly, Armin Kemna, director Design Support at Elmos Semiconductor adds, "We are seeing up to 10% reduction in gate count simply by using the latest release of Design Compiler. In addition, technology links between Design Compiler and IC Compiler provided early insight into physical challenges and helped us stay on schedule."

Design Compiler includes new optimisation technologies that monotonically reduce design area and leakage power; these area optimisations operate on new or legacy design netlists, with or without physical information and at all process nodes. Utilising this new capability, in conjunction with new congestion optimisations, designers can significantly reduce die area and ease design closure without impacting any other QoR metrics. New RTL analyses and cross probing capabilities accelerate design schedules.


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