Circuit matching and analog layout
Analog circuits often use structures like differential pairs and current mirrors, where the matching of device characteristics such as the threshold voltage Vt is important. Circuits using these structures with device threshold differences of a few millivolts or less can determine the performance and yield of a design.
The threshold difference between a pair of (otherwise identical) MOS devices is due to the variations in number of doping atoms in the channel. This difference has been shown to be proportional to the inverse square root of the channel area,[1] and it reduces with decreasing gate oxide thickness.
However, matching also requires careful layout techniques to minimize the differences in device parameters due to distance, lithography variations, rotation, process variations, biasing, and temperature gradients on the chip.
One common matching technique is known as common centroid. In this case, two devices to be matched are split into several fingers and placed in a pattern, as shown in Figure 1.
Figure 1: A typical common-centroid layout pattern of two devices, A and B.
The key points are that the centroids of each device should coincide, the devices should be symmetrical, their orientation should be the same, and the array should be as compact as possible.[2] Because end elements have different boundary conditions, dummy devices are often added at the ends of the rows to further reduce mismatch effects.
For the layout designer, manually placing devices to form common-centroid structures is tedious. It is possible, with suitable programming in a scripting language, to generate parameterized cells for automatically creating placed devices in a common-centroid pattern. However, routing them manually to connect up the gates, sources, and drains is time consuming, and automatic routers do not do a good job.
Figure 2: An automatically placed and routed common centroid device.
Ideally, the layout tool should be able to recognize structures that need common-centroid layout automatically and generate the correct placement and routing to give optimal common-centroid layouts, as shown in Figure 2. This would free analog layout engineers of one of the more tedious parts of their job and allow greater productivity.
References:
[1] "Transistor matching in analog CMOS applications," Marcel J.M. Pelgrom, Hans P. Tuinhout, Martin Vertregt, IEDM 1998.
[2] "The Art of Analog Layout", Alan Hastings 2006.
Keith Sabine, product manager for analog solutions at Pulsic Ltd. (Bristol, England), has 35 years of experience in the semiconductor and EDA industries, starting out as a bipolar designer at Fairchild Semiconductor before moving into CMOS process development and characterization at Plessey Semiconductors. His EDA career has included time at Cadence, Simplex, Apache, and now Pulsic.
This article first appeared on EE Times’ Planet Analog website.
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