Clock buffer delivers low jitter to optimize noise performance in ultra-high-speed data converters
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eeNews Europe
The 1.65-GHz AD9508 clock buffer is designed for communications, instrumentation, defence and aerospace equipment that require ultra-high-speed data conversion with optimum SNR (signal-to-noise ratio) performance. The device has four dedicated output dividers with bus-programmable division (integers up to 1024) and phase delay, and automatic synchronisation.
The dividers also have pin-strapping capability for hardwired programming at system power-up. The AD9508 supports up to four differential, or eight single-ended outputs and three logic levels: LVDS (1.65 GHz), HSTL (1.65 GHz), and CMOS (250 MHz).
www.analog.com/en/clock-and-timing/clock-generation-and-distribution/ad9508/products/product.html
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