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Clock generators feature low jitter, low power and NCO in a compact package

Clock generators feature low jitter, low power and NCO in a compact package

New Products |
By eeNews Europe



“With our new clock generators, designers no longer need to rely on expensive oscillators to get high speed output clocks with outstanding jitter performance, flexibility and dependable performance,” said Maamoun Seido, vice president and business unit manager of Microsemi’s timing products. “The addition of these new generators, coupled with the launch of our first clock buffer family last year, further solidifies our leadership position in timing and synchronization semiconductor solutions. This market segment remains a key area of focus and investment for Microsemi.”

Traditionally, fundamental speed oscillators have a limitation in the range of 50 MHz and third overtone options have a limitation  in the range of 150 MHz. Designers depend on analog phase locked loops (APLLs) to multiply low frequency signals and generate the desired high frequencies. The quality of the output signal depends on the performance of the APLL. To achieve high performance, designers are forced to use high cost APLLs, as high performance drives a higher APLL cost.

Microsemi’s new, small footprint, high-performance clock generators can generate high frequency output clocks with very low jitter, low power consumption. The dual-channel or single-channel variants feature numerically controlled oscillators (NCO) that can generate any frequency with fine tunability of 0.1 ppb. The new clock generators improve reliability, simplify product development efforts, lower bill-of-material costs and are well-suited for cost-sensitive applications with high performance requirements.

Microsemi’s ZL30240 and ZL30241 feature two to four independently programmable outputs with support for multiple frequencies (up to 940 MHz) and multiple signal formats to facilitate flexible rate conversions’
Up to two synthesizers enabled the concurrent use of two independent frequency families.

The devices manage jitter as low as 0.27 picoseconds (rms) to meet tight jitter budgets of PHYs.

The ZL30240 and ZL30241 are low power consumption devices featuring less than 300 milliwatts per channel.

Visit Microsemi at www.microsemi.com

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