Clock-tree design made easy
For Internet infrastructure applications such as high-speed networking, telecommunications and data center equipment, the selection of timing components and clock tree designs is crucial since timing ICs provide low-jitter timing references for high-speed 10/40/100G data applications.
When specifying clock trees for their applications, hardware designers must ensure critical jitter performance parameters are met with sufficient margin with the minimum number of timing components. Choosing the optimal combination of clocks, oscillators, jitter attenuators and buffers can be a daunting and time-consuming task for a given Internet infrastructure application.
Leveraging Silicon Labs’ DSPLL and MultiSynth technologies, the web-based Clock Tree Expert tool frees developers from the burden of designing clock trees by recommending the optimal combination of highly integrated, low-jitter, frequency-flexible clocks and oscillators required to consolidate timing BOM into the fewest number of components.
With the Clock Tree Expert, users simply enter the required frequencies, number of clocks and desired signaling format, and the tool generates a recommended clock tree in seconds using the minimum number of timing components.
Experienced users can also use the tool’s “Build Your Own” environment to design clock trees to their exact specifications. The Clock Tree Expert then guides the user to find the optimal timing ICs, save and share clock tree designs, generate a BOM list and order samples.
In addition to streamlining clock tree design, the Clock Tree Expert provides instant access to the manufacturer’s comprehensive timing product information and data sheets.
Customize buttons automatically take developers to Silicon Labs’ suite of timing customization tools, which can be used to generate custom crystal oscillator (XO), voltage-controlled oscillator (VCXO), CMEMS oscillator and CMOS/differential clock generator part numbers.
Visit Silicon Labs at www.silabs.com/timing
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