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Cloud-based RTL tool for embedded RISC-V cores

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By Nick Flaherty

Western Digital is not a name you expect to be supplying open source processor cores. But its SweRV cores, based on the RISC-V open source architecture, are aimed at deeply embedded system-on-chip applications.

The SweRV cores available through another RISC-V core supplier, Czech processor tool designer Codasip, which has its own customisable RISC-V cores. Codasip has just done a deal to use the cloud-based SystemVerilog RTL Simulation Platform from Metrics Design Automation with SweRV support package.

The integration provides a very easy-to-use and inexpensive way for ASIC designers to verify modifications and enhancements they make to the SweRV embedded processor IP. The latest EH2 and EL2 32bit SweRV cores developed by Western Digital (WD) were added to the SweRV Support Package in June alongside the EH1 core.

The cloud-based simulation tool is the only RTL simulator available with a SaaS business model—users simply pay for use as a service. The implementation of Metrics simulator in the Cloud provides massive scalability so regression tests can run in parallel to complete in hours, not days.

“Western Digital do a lot of inhouse design for their storage products so you don’t get to see a lot about the designs but they have a lot of expertise in the processor areas. They embraced RISC-V early on and made a very significant commitment to it and invested in the Codasip series A funding,” said Roddy Urquhart, senior marketing director at Codasip.

​“In terms of RISC-Vs strategy they wanted to open source some of the technology. In December of last year they had been discussing how best to get their three high performance embedded cores to market. RTL on its own is not sufficient to deploy a core in an SoC,” he said.

Next: RISC-V SweRV support package 


“We agreed on the SweRV support package approach where we would provide all the thing we would need. There’s the SDK but there’s also the whole EDA side, you need simulation, synthesis flows, static tools for RTL analysis so we created the SweRV support package. Some of the components are open source, with a free version for academia but for people doing chip designs there is the commercial version.”

“We also provide professional customer support, so we make it a lot easier to deploy a SweRV core and we support people in using our flows,” he said. “We see this as an opportunity to make money in a different way and for WD it means that people interested in their cores have a straightforward path.”

Last month Codasip launched its first application processor, the Bk7. The 64bit core has a 7-stage pipeline and memory management unit (MMU) and like the previous Bk core designs, it has been designed in the Codasip Studio processor design system. This means that its architecture can be readily modified to create application-specific processors with all the features needed for running embedded Linux. This will be the cornerstone for further application processor developments as well as future versions that support symmetric and heterogenous multiprocessing.

“Our cores are classic low and medium complexity embedded cores,” said Urquhart. “The Bk7 is a 64bit app core running Linux. The SweRV cores are high performance integer cores with nine stage pipelines so they can deliver a lot more integer performance. They are not suitable of other things such as Linux as they have only one privilege mode, so its complementary,” he said.

“For us, we see promoting the WD cores alongside ours is the way we can make a commercial success of the SweRV support package. There are different application areas where one or other would be appropriate. For high performance storage or networking the SweRV cores are an excellent fit, while for Linux the Bk7 and a smaller Bk3 core for wireless might be appropriate,” he said.

“There’s no point in developing something similar ourselves. These neatly fit above our existing 32bit cores. The way the cores have been developed is slightly different – the SweRV cores are handwritten RTL while Codasip has generated cores from a high level description in our HDL. So if you want to rapidly create a custom variant you can use our tools. We already have orders from people that want extensions to the SWERV cores. AS we know quite a bit of processor customisation we can provide as a service ways of extending the SweRV cores by modifying the RTL and verification environment.”

This is where the Metrics deal fits in. “The popularity of RISC-V and in particular the SweRV open source processor IP has been impressive,” said Doug Letcher, CEO of Metrics. “We are excited to partner with a leading RISC-V embedded processor IP vendor such as Codasip to deliver better usability, accelerated verification, and much more affordability of RTL simulation tools to the ASIC and SoC design community.”

This boosts the use of SweRV. “Our customers are advanced fabless semiconductor companies – it’s a make vs buy decision – you could use in house expertise for in house EDA flows or you can come to us and it works out of the box and you save that internal investment,” said Urquhart. “For me it’s more a question of where your core competence is. We are also maintaining the SweRV support package as there are different releases of the cores and new EDA releases as they come out. To me, that just allows design teams to focus on their design rather than running about flows to specifically support design flows.”

www.codasip.com; www.metrics.ca

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