CMOS-compatible supercaps pack up to 214W cm−3

CMOS-compatible supercaps pack up to 214W cm−3

Technology News |
By Julien Happich

The supercap structure consists in microchannels etched in bulk silicon, whose sidewalls are treated to host a hybrid nanomaterial electrode consisting of Porous Silicon (PS) coated with a few nanometre thick titanium nitride layer (through an atomic layer deposition (ALD) process). The lateral thickness of the coated porous silicon layer as well as the length of the channels determine the capacitance of the whole structure expanding laterally within the chip substrate.

Conformal coating of PS is not straightforward due to very high aspect ratios which can reach 1:1000 and above, explain the researchers in a paper made available on Science Direct and to be published in Nano Energy this summer. But they tuned their ALD process to deposit a 10nm thick homogeneous layer of TiN inside the PS matrix. They then added contact pads and filled the trenches with a liquid electrolyte to obtain very efficient electrochemical double layer capacitors (EDLC) with almost ideal characteristics. This is thanks to the good electrochemical properties of TiN and the large area of the PS matrix, notes the paper.

What’s more, the whole manufacturing process does not exceed 450°C, making it CMOS compatible, in effect turning the unused bulk silicon of planar chip designs into useful integrated energy storage pockets.

Characterizing a few prototypes, the researchers report a very high specific capacitance of 15Fcm−3, an energy density of 1.3mWh cm−3, and a power density up to 214W cm−3, all combined with a stability exceeding 13,000 cycles (Prunnila later added that so far the maximum number of recorded cycles had been 50,000 only limited by the measurement time, with no observable degradation for the porous Si-TiN electrode material.

In-chip PS–TiN supercapacitor. (a) SEM picture of the trenches separating the electrodes. (b) Schematic illustration of the cross-section of two opposite electrodes of a ready device (TiN coated PS layer and the aluminium contact pads on the back side are also present). (c) Higher magnification SEM picture of the porous regions. (d) Device trench side and (e) the metallization side containing aluminium contacts for supercapacitor electrodes. (f) Cyclic voltammetry curve at 100 mV/s (inset) and capacitance retention.

And for the first time, silicon-based a micro-supercapacitor competes with leading carbon and graphene based devices in power, energy and durability, concludes the paper.

“The idea is to add these supercapacitors as a backend process, using the remaining bulk of the silicon substrate as free real-estate to stack multiple supercapacitors laterally”, explained Dr. Mika Prunnila, Research Team Leader for Nanoelectronics at VTT, “but you could also envisage to connect multiple supercaps from 3D die stacks” he added.

The prototypes were designed with different thicknesses of porous silicon layers within the trenches, only a few micron thick up to 7µm, but increasing that thickness could dramatically increase the capacitance values. As an extrapolation, the researcher estimates that with 20µm thick PS and the same electrode configuration, the device could pack 50mF cm–2.

Electrolyte channels on a 150mm wafer.

Prunnila sees commercial opportunities by licensing the IP for the design of embedded passive devices, or even to build standalone surface-mount silicon supercapacitors.

Now, the prototypes were uncapped, as shown on the illustrations.

“These prototypes were proof of concept, but next we need to work on sealing the devices, we are also exploring various solid-state electrolytes” Prunnila concluded.

Such micro-supercapacitors would nicely tie-up with energy-harvesting management ICs for autonomous sensor networks, wearable electronics and other IoT applications.


Visit VTT Technical Research Centre of Finland Ltd at


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