CMOS phased array transmitter for 2D beam steering at 300GHz

CMOS phased array transmitter for 2D beam steering at 300GHz

Technology News |
By Nick Flaherty

Researchers in Japan have developed a phased array transmitter design in CMOS that overcomes common problems of the technology in the 300 GHz band.

The team at Tokyo Tech see the 300GHz CMOS phased array transmitter being used for body and cell monitoring, radar, 6G wireless communications, and terahertz sensors.

Many researchers are developing 300 GHz transmitters/receivers to capitalize on the low atmospheric absorption at frequencies above 250GHz, as well as the potential for extremely high data rates. However the power falls off very quickly at these high frequencies, so transmitters must compensate by achieving a large effective radiated power. As yet, no 300 GHz-band transmitter manufactured via conventional CMOS processes has simultaneously realized high output power and small chip size.

The team led by Professor Kenichi Okada from Tokyo Institute of Technology (Tokyo Tech) and NTT used 64 radiating elements, which are arranged in 16 integrated circuits with four antennas each.

As the elements are arranged in three dimensions by stacking printed circuit boards (PCBs), this transmitter supports 2D beam steering so that the transmitted power can be aimed both vertically and horizontally, allowing for fast beam steering and tracking receivers efficiently.

The Vivaldi antennas can be implemented directly on-chip and have a suitable shape and emission profile for high frequencies.

An important feature of the proposed transmitter is its power amplifier (PA) architecture. By placing the amplification stage right before the antennas, the system only needs to amplify signals that have already been conditioned and processed. This leads to higher efficiency and better amplifier performance.

The researchers also addressed a few common problems that arise with conventional transistor layouts in CMOS processes, namely high gate resistance and large parasitic capacitances. They optimized the layout by adding additional drain paths and vias and by altering the geometry and element placing between metal layers.

“Compared to the standard transistor layout, the parasitic resistance and capacitances in the proposed transistor layout are all mitigated,” said Prof. Okada. “In turn, the transistor-gain corner frequency, which is the point where the transistor’s amplification starts to decrease at higher frequencies, was increased from 250 to 300 GHz.”

The team also designed and implemented a multi-stage 300 GHz power amplifier to be used with each antenna with impedance matching between stages.

“The proposed power amplifiers achieved a gain higher than 20 dB from 237 to 267 GHz, with a sharp cut-off frequency to suppress out-of-band undesired signals,” said Okada.

The proposed amplifier also achieves a noise figure of 15 dB which was evaluated by the noise measurement system in 300GHz band and tested in through both simulations and experiments.

The transmitter achieved a data rate of 108 Gb/s via on-PCB probe measurements, substantially higher than other state-of-the-art 300GHz transmitters.


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