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CMP offers STMicroelectronics analog 130-nm H9A CMOS process for prototyping next generation SoCs

CMP offers STMicroelectronics analog 130-nm H9A CMOS process for prototyping next generation SoCs

Technology News |
By eeNews Europe



The process offers a large panel of analog and digital devices.  The diffusion of the silicon wafers will take place at the ST plant in Rousset, near Aix-en-Provence (France). ST is releasing this process technology to third parties as a foundry service for a well-established analog platform and for new developments in the More than Moore applications such as energy harvesting, autonomous intelligence, and home-automation integrated systems.

The introduction in CMP’s catalog of ST’s H9A (and its derivative H9A_EH) process builds on the successful collaboration that has allowed universities and design firms to access leading-edge and previous CMOS generations including 28 nm CMOS, 45 nm (introduced in 2008), 65 nm (introduced in 2006), 90 nm (introduced in 2004), and 130 nm (introduced in 2003) through the ST Site of Crolles.  CMP’s clients also have access to 28 nm FD-SOI, 65nm SOI and 130 nm SOI (Silicon-On-Insulator), as well as 130 nm SiGe processes from STMicroelectronics. More than 200 universities and companies have received the design rules and design kits for the ST 65 nm bulk and SOI CMOS processes.

Since CMP started offering the ST 28 nm CMOS bulk technology in 2011, some 100+ universities and microelectronics companies have received the design rules and design kits, and 30+ integrated circuits (ICs) have already been manufactured. Since CMP introduced the 28 nm FD-SOI, 30+ universities and microelectronics companies have received the design rules and design kits.

“There has been a great interest in designing ICs using these processes, with about 300 projects having been designed in 90 nm (phased out in 2009), and more than 350 already in bulk 65 nm,” said Bernard Courtois, Director of CMP. “In addition, more than 60 projects have already been designed in 65 nm SOI and many top universities in Europe, USA/Canada and Asia have already taken advantage of the collaboration between CMP and ST.”

The CMP multi-project wafer service allows organizations to obtain small quantities – typically from a few dozens to a few thousand units – of advanced ICs. H9A design rules and design kits are now available for universities and microelectronics companies and the first requests are already being answered. A run is forecast for September 2013 to carry the first contributions.

ST will propose ULP/ULQC devices (Ultra Low Power, Ultra Low Quiescent Current) in the next Design Kit (DK) generations as this is a requirement for harvesting low-energy sources and for long-life autonomous intelligent systems. One of the world’s most advanced 200mm wafer plants, ST’s Rousset site has become a center of excellence that provides a technology designed for low consumption and slow duty cycles and attracts innovating contributions and collaborations from the academic research environment  While providing additional features in the near future, compatibility with current DK and process will be granted regardless of the technology evolutions in order to keep a stable offer and allow medium- and long-term planning to interested universities and design firms.

The cost of the H9A CMOS process has been fixed to 2200 Euro/mm².

Visit STMicroelectronics at www.st.com

Visit CMP at https://cmp.imag.fr

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