Codasip hits out at RISC-V processor verification
European RISC-V processor designer Codasip has hit out at the quality of competing designs as it signs a deal with Siemens EDA to use the OneSpin tool for formal verification.
“The poor verification of some RISC-V IP is frankly shocking,” said Rupert Baines, CMO at Codasip. “Developers have legitimate concerns about the quality of RISC-V IP that’s holding back its adoption. Higher quality and formally proven RISC-V IP will help it to cross the chasm and massively increase its adoption.”
Siemens bought OneSpin, based in Munich, last year, for the focus on verification. Processor verification has been a key part of the development of the configurable Codasip cores to ensure high quality designs using the RISC-V open instruction set architecture (ISA), and the company uses Siemens EDA (formerly Mentor Graphics) as its primary EDA tool flow. The company has two billion cores in use, mostly with tier one customers.
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“We are pleased to collaborate with Codasip to help ensure the high quality of their RISC-V Processor IP, as well as to establish optimized solutions for our mutual customers,” said Neil Hand, strategy director for the IC Design Verification division of Siemens EDA. “The world-class technology of our OneSpin formal verification tools including the OneSpin RISC-V verification solution, together with Codasip’s innovative IP, is key for IC designers to deliver high-quality products to market quickly.”
Codasip’s Director of Verification, Philippe Luc, added, “We are very proud of our own rigorous approach to verification with a strong in-house verification team – our own extremely thorough internal testing methodologies, combine with best-in-class third-party tools. As part of this, we’re delighted to use OneSpin technology from Siemens EDA, which is a key partner for Codasip – we look forward to a closer and productive relationship.”
www.codasip.com; www.riscv.org.
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