Codasip, IAR show dual-core lockstep for RISC-V safety designs
Codasip and IAR have developed a dual-core RISC-V processor that operates in lockstep, opening up a route to ISO 26262-qualified embedded applications based on the versatile Codasip L31 core.
Other groups, particularly Fraunhofer,, have developed safety certified RISC-V cores, but the collaboration of Codasip with IAR’s safety-certified version of the development toolchain provides a commercial path for automotive chip developers.
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Codasip’s dual-core lockstep reference design implements two Codasip L31 cores in a dual-core fault detection subsystem. The L31 low-power, general-purpose, embedded RISC-V core provides a balance between performance and power consumption. It can be easily customized with Codasip Studio tools for applications from IoT devices to industrial and automotive control, or as a deeply embedded core in a larger system.
The functional safety edition of IAR Embedded Workbench for RISC-V is certified to ten different standards by TÜV SÜD, including ISO 26262. IAR offers guaranteed customer support for the duration of the support contract with validated service packs, and regular reports of known deviations and problems. IAR Embedded Workbench for RISC-V currently supports the off-the-shelf version of the Codasip L31 core as well as the dual-core lockstep reference architecture.
“The automotive market is shifting rapidly driven by increased needs for accelerated innovation with reduced complexity and cost. RISC-V is offering exactly this,” said Jamie Broome, vice president of automotive business and product at Codasip.
“Codasip is delivering custom compute with full ownership and control. Through our collaboration with IAR, we provide automotive companies with a straightforward solution for certifying their products for ISO 26262 and other functional safety and security standards,” he added.
Codasip and IAR are showcasing the design at Embedded World (EW2023) this week in Germany.
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