Codasip joins OpenHW to push RISC-V verification
German RISC-V core designer Codasip has joined the OpenHW group to push for advances in the verification of RISC-V cores.
Codasip has highlighted issues with verification of cores designed with the open source RISC-V instruction set architecture. Codasip plans to contribute supporting IP, tools, and methodologies
The OpenHW Group is a non-profit global organization driven by its members and individual contributors to enable hardware and software designers to collaborate in the development of open-source cores, IP, tools and software. OpenHW provides an infrastructure for hosting high-quality open-source hardware developments in line with industry best practices.
It has a Cores Task Group developing the roadmap and related open-source IP for the cores the CORE-V Family of open-source RISC-V processors, based on technology from ETH Zurich in Switzerland. A Verification Task Group is working on verification testbench environments for the family of cores and IP blocks.
Codasip is pushing for the establishment of agreed strategies and standards to ensure the quality of RISC-V cores continues to improve. OpenHW Group is an active member of RISC-V International with a shared belief in the importance and prioritization of commercial-grade verification for RISC-V.
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“We acknowledge the importance of OpenHW Group’s goals of providing wider access to high-quality cores and will work towards these goals by sharing our expertise in verification but potentially also in other areas where we see a need to step up efforts for the shared benefit of the processor industry.,” said Mike Eftimakis, Codasip VP Strategy and Ecosystem.
“I am excited to welcome Codasip as a strong addition to OpenHW Group,” said Rick O’Connor, President and CEO of OpenHW Group. “The OpenHW ecosystem provides an infrastructure for hosting high-quality open-source HW developments in line with industry best practices. Codasip puts significant emphasis on the importance of processor verification for RISC-V. As a leader in RISC-V processors, Codasip’s role will be crucial in setting industry standards and collaborating on projects with the 90+ members of OpenHW Group.”
“In the strong and growing RISC-V community, everyone supporting the open standard benefits us all. We see the roles of open-source IP and commercial IP as complementary and though we sell our cores, we also see open source as a critical part of the ecosystem and for the success of RISC-V,” said Eftimakis. “We acknowledge the importance of OpenHW Group’s goals of providing wider access to high-quality cores and will work towards these goals by sharing our expertise in verification but potentially also in other areas where we see a need to step up efforts for the shared benefit of the processor industry.”
Edward Wilford, Senior Principal Analyst, IoT Hardware at Omdia said: “There is no question that a set of transparent, consistent and meaningful standards could go a long way towards improving the overall level of quality expected in the industry. It is crucial that ‘open source’ doesn’t in any way come to signify ‘anything goes’, especially with the increasing attention vendors, manufacturers and consumers are paying to chip and device security. It’s fair to say an SoC, a network, or a sensor array is only as secure and as capable as its weakest element, so any initiative that adds trust to the ecosystem, whether commercial or open-source, should be welcomed.”
Formed in 2014 and headquartered in Munich, Germany, Codasip currently has R&D centres in Europe and sales representatives worldwide.
www.codasip.com; www.riscv.org; www.openhwgroup.org
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