Codasip licenses RISC-V core for headset chip
German processor core design Codasip has licensed one of its RISC-V cores to a Chinese sensor designer for an intelligent headset
Nanjing Tianyi Hexin Electronics will use Codasip’s L30 (originally Bk3) RISC‑V core for their TWS headset and intelligent wearable chip design.
Tianyi Hexin, founded in 2014, is a leading optical and high-precision capacitive sensor design company in China designing high-precision ADCs for sensors.
Tianyi Hexin will use the L30 RISC-V processor in multi-point, high-precision capacitive sensing chip for contact and non-contact multi-touch and gesture recognition. The L30 core will provide control functions to the overall system, including sliding, double-clicking, long-press, and other operations to create a comfortable control experience for customers using the TWS headset and other intelligent wearable devices based around the Hx9131 chip.
“The integration of high-precision sensing technology and RISC-V architecture provides us with the optimal flexibility, control, and performance,” said Dingkai Zuo, Vice President of Engineering at Tianyi Hexin. “A microcontroller based on Codasip L30 can adapt to various application scenarios and provide more flexible solutions.”
The Codasip L30 processor is based on the RISC-V open instruction set architecture (ISA). It is optimized for low power and area efficiency. It has a single 3-stage processor pipeline architecture, optional caches, optional Floating Point Unit, Multiplication and Division, JTAG and RISC-V debug, and industry standard bus interfaces (AMBA).
It also includes support for privilege-mode and memory protection via standard RISC-V PMP, making it an attractive alternative to legacy, proprietary microcontroller cores. L30 is fully configurable and extensible in compliance with the RISC-V standard..
www.tianyihexin.com; www.codasip.com
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