Codasip to exhibit CHERI security, HW/SW co-optimization
German RISC-V processor developer Codasip GmbH (Munich, Germany) is set to demonstrate CHERI memory protection and HW/SW co-optimization at the Embedded World exhibition in Nuremberg, Germany.
CHERI stands for Capability Hardware Enhanced RISC Instructions and Codasip plans to show its custom compute offering in hall 4, stand 4-368. Visitors will get to see fine-grained memory protection with CHERI. This technology, invented at Cambridge University and brought to commercial implementation by Codasip, actively prevents the most common cyberattacks with the potential of eliminating approximately 70 percent of vulnerabilities documented in the Common Vulnerabilities and Exposures (CVE) program.
Codasip is adding built-in fine-grained memory protection to its recently launched 700 processor family by extending the RISC-V ISA with CHERI-based custom instructions.
In addition, the company will show how to profile an embedded application to identify bottlenecks in the code and how custom instructions can be added to optimize the hardware to improve the application’s performance. Codasip claims the potential gains from HW/SW co-optimization include:
- 2x performance gain running the SHA512 cryptographic hash algorithm
- 2.5x speedup and 30 percent reduction in power consumption for AI/ML workloads
As part of the Embedded World conference program, Codasip’s CTO Zdenek Prikryl will present the session “Customized RISC-V in a simple game console” (Session 8.5 SYSTEM-ON-CHIP (SoC) DESIGN / RISC-V 2) on Thursday 11 April.
Related links and articles:
News articles:
Codasip delivers first commercial CHERI processor using RISC-V
CEO interview: MIPS’ Sameer Wasson on a RISC-V reboot
AutoCHERI starts cybersecurity penetration testing
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