The EV Group (EVG) in Austria has demonstrated a complete process flow for collective die-to-wafer (D2W) hybrid and fusion bonding with sub-2μm placement accuracy fro 3D packaging.
The process uses EVG wafer bonding technology and processes, as well as existing bond interface materials. This breakthrough was demonstrated at EVG’s Heterogeneous Integration Competence Centre and represents a key milestone for accelerating the deployment of heterogeneous integration (HI) in next-generation 2.5D and 3D semiconductor packaging.
The centre serves as an open access innovation incubator to help customers accelerate technology development, minimize risk, and develop differentiating technologies and products through advanced packaging.
Developers of systems for artificial intelligence, autonomous driving, augmented/virtual reality and 5G are all looking at heterogeneous integration (HI) for manufacturing, assembly and packaging of multiple different components or dies with different feature sizes and materials onto a single device or package to increase performance on new device generations.
Collective D2W bonding is an essential HI process step that enables functional layer and known good die (KGD) transfer to support cost-efficient manufacturing of new types of 3D-ICs, chiplets, and segmented and 3D system on chip (SoC) devices.
“For more than 20 years, EVG has provided process solutions and expertise to support the advancement of HI, including D2W bonding, where our technology has been successfully implemented in high-volume manufacturing applications,” said Markus Wimplinger, corporate technology development & IP director for EV Group.
“Our Heterogeneous Integration Competence Center, which is supported by our worldwide network of process technology teams, enhances our capabilities in this critical area by providing a foundation for customers and partners working with EVG to develop new 3D/HI solutions and products,” he said. “Among these is our new collective D2W bonding approach, where we have demonstrated the ability to perform all key process steps in-house with high placement accuracy and transfer rate using our existing wafer bonding and debonding, metrology and cleaning process equipment along with select third-party systems from our development partners. We’d like to thank our partners for their role and support in enabling this important achievement. A special thanks goes to IRT Nanoelec and CEA-Leti, which both provided the substrates that were used in this demonstration.”
Bonding multiple dies to a wafer in a single process requires a reliable local multiple-dies bonding technology as well as state of the art optical alignment accuracy. This has to provide electrical and photonic connections for signal input and output, power input, and voltage control as well as thermal dissipation and the physical protection required for increased product reliability.
The process uses a customised temporary carrier with alignment features to place known good dies (KGD) on the carrier and enable die processing prior to the final bonding process. Such carriers with KGDs were successfully processed using direct bonding, hybrid bonding, adhesive bonding and metal bonding using as bonding partner different substrate materials including silicon and III-V semiconductors. The process success was verified by the final transfer rate, scanning acoustic microscope imaging and TEM cross section analysis.
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