Comparing switching topologies for solar inverter designs
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By Damijan Zupancic, Application Marketing Manager Solar & ESS at Infineon Technologies
The increasingly urgent requirement to reduce carbon emissions has caused a surge in the popularity of renewable energy sources such as solar inverter systems. These require lightweight, efficient, and high power-density inverters which can be interconnected to the grid.
Traditionally, insulated gate bipolar transistors (IGBT) have been the preferred option for both three-phase and single-phase (≤10 kW) solar inverters while silicon super-junction (SJ) MOSFETs (600/650 V) have also been employed in some single-phase applications. However, IGBTs and Si SJ MOSFETs both limit the efficiency and power density that solar inverters can attain.
More recently, two alternative approaches have begun to attract attention – the first involves replacing IGBT and silicon SJ MOSFETs with wide bandgap devices like silicon carbide (SiC) MOSFETs while the second approach replaces traditional circuit topologies with a multilevel topology that can continue to employ lower voltage silicon MOSFETs. In this article, Infineon discusses the relative merits of each approach and shows how they can both be used to achieve efficiency levels of up to 99% in solar inverter designs.
Option 1: SiC MOSFETs replace IGBTs and Si SJ MOSFETs
Due to their high switching losses, it only makes sense to use IGBTs in applications with switching frequencies below 20 kHz. SJ MOSFETs have high reverse recovery charge (Qrr), slow body diode, and relatively high RDS(on) which negatively impact their operation in inverter applications. These drawbacks limit the operating efficiency and power density achievable using either of these devices in typical single-phase solar inverter designs to a maximum of 98%.
On the other hand, SiC MOSFETs feature fast body diodes, have very low Qrr, and exhibit lower switching losses than IGBTs. Infineon’s 650V CoolSiC MOSFETs can replace IGBTs and Si SJ MOSFETs without the requirement to modify the circuit topology used in an inverter. SiC MOSFETs can switch at higher frequencies, which means smaller filter components (inductor, capacitor) can be used and this has the benefit of reducing the size and weight of the inverter enclosure, delivering cost savings in line with increasing power levels. SiC MOSFETs also have significantly lower switching losses than SJ MOSFTETs.
Figure 1 shows how Infineon’s 650V CFD7 CoolSiC MOSFETs against alternative SJ MOSFETs under identical operating conditions and for the same RDS(on).
Figure 1 Comparing figures-of-merit for SiC and SJ MOSFETs at the same operating conditions and RDS(on)
Figure 2 shows the conduction losses for three best-in-class switches from Infineon, including the IKW30N65H5 650V TRENCHSTOP 5 IGBT, the IPW60R031CFD7 600V CoolMOS CFD7 silicon SJ MOSFET and the IMW65R027M1H 650V CoolSiC MOSFET at junction temperatures of 25°C (left) and 125°C (right).
It is clear that while the conduction losses of IGBTs are significantly higher than for the other devices at 25 °C, losses do not increase further as the junction temperature increases to 125 °C. It can also be seen that the conduction losses of the SJ MOSFET at 125°C are twice those at 25°C. Finally, losses in the SiC MOSFET only increase by approximately 20% over the entire temperature range, giving an advantage over silicon MOSFETs in high current, high-temperature applications such as a solar inverter.
Figure 2 Comparing device conduction losses at 25°C (left) and 125°C (right)
Scenario 2: Changing to multilevel circuit topologies
Topologies like Heric, H6, H6.5, employing 650 V IGBT and 650 V SJ MOSFET devices are commonly used in conventional single-phase solar inverter designs. However, a new multilevel topology based on medium-voltage MOSFETs (150 V to 200 V) has emerged as potential alternative (Figure 3).
Figure 3 Replacing a two-level topology with a multilevel topology
Compared to the conventional approach, the multilevel topology has the advantage of requiring a much smaller inductor and capacitor, thus enabling a higher power density solar inverter design that requires less cooling.
Furthermore, while adopting a multilevel approach requires using more medium voltage MOSFETs, the heat dissipated due to power losses is distributed across more devices, simplifying thermal management, and potentially enabling inverter designs that don’t require fans or heatsinks. Semiconductor components typically contribute less than 10% of the overall bill of materials (BOM) in a single-phase string inverter (≥ 3 kW).
In comparison, the cooling system and passive components (capacitors and inductors), contribute 30-40% of the overall cost. In addition, while the price of semiconductor components tends to reduce over time, the cost of passive components is relatively static. Therefore, for existing single-phase solar inverters operating at power levels exceeding 3 kW, moving to a multi-level topology (which uses smaller passives and more semiconductor devices) makes sense because it can deliver cost savings. Inverters with higher power ratings can realize even greater cost savings by moving to a multi-level topology.
Another significant advantage of multilevel inverters is that the lower power loss per device allows smaller MOSFETs in surface mount (SMD) packages to be employed. SMD packages are ideally suited for use in automated pick and place processes, reducing system assembly costs. Furthermore, smaller packages have lower inductance, which helps to improve switching performance at higher frequencies. Another significant advantage of multilevel inverters is their scalability to higher power levels using an almost identical design and board layout. However, it should be noted that compared to conventional topologies, multi-level inverters require a higher number of gate drivers and isolated power supplies.
A 4 kW MV MOSFET multilevel solar inverter with no fan or heatsink
To investigate the performance of the proposed multi-level topology, Infineon built a 4 kW, five-level single-phase flying-capacitor-based active neutral point clamped multilevel inverter demonstration board (Figure 4) based on the design specifications shown in Table 1. An advantage of this multi-level design was it could use 150V 9.3 mΩ OptiMOS 5 150 V (BSC093N15NS5) MOSFETs, even though the bus voltage was 400 VDC.
Table 1 Design specifications for the proposed multi-level inverter
Figure 4 Schematic of the five level inverter design
Figure 5 shows the efficiency of this design measured with respect to output power. It delivered a maximum efficiency of 99.1% at ~2kW of output power. At full load (4 kW), it continued to deliver exceptionally high efficiency (98.7%) percent. A heat map of the board at full output power showed that the maximum component temperature measure was less than 85 ˚C. These efficiency and temperature figures explain why this multilevel inverter can work continuously without the requirement for a heatsink or fan
Figure 5 Efficiency vs. output power for the five level inverter (@ 40 kHz switching frequency)
Conclusion
While replacing silicon-based devices with SiC MOSFETs is easier than changing the inverter topology, this approach does not improve efficiency and power density as much as the multilevel approach, meaning a heatsink is still required at lower power levels and forced cooling may be required at higher power ratings (> 5 kW). While a multilevel topology is more complex, it can deliver in excess of 99% efficiency and high power density, making the design effort worthwhile.
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