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Complete clock-tree synthesizers and rate converters offer lowest jitter

Complete clock-tree synthesizers and rate converters offer lowest jitter

New Products |
By Jean-Pierre Joosting



Featuring four independent frequency families, best jitter performance, up to 10 differential or 20 single ended configurable outputs and two fractional-N analogue phase locked loops (APLLs) with a fractional and integer divider, these miClockSynth devices can create a complete clock tree. The new devices can replace a number of multipliers, synthesizers and oscillators on the board, simplifying design. The products also feature an intuitive graphical user interface (GUI) and the ability to create factory pre-programmed devices with ease using Microsemi’s web tool, miClockDesigner.

In addition to the new devices’ ultra-low output jitter of 170 femtoseconds (fsecv) root mean square (RMS), they also offer any-rate frequency conversion—with any input frequency ranging from 10 MHz to 1.2 GHz to any output frequency less than 1 Hz and up to 1 GHz. They feature a highly precise numerically controlled oscillator with steep output frequency per APLL or fractional/integer-N divider with better than 0.01 parts per billion (ppb) resolution. The devices’ output format is configurable, with native LVDS, LVPECL, HCSL, 2xCMOS or HSTL per output reducing the number of termination components. The device also features spread-spectrum modulation mode that meets PCIe market requirements.

Microsemi: www.microsemi.com

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