Complete DDR5/LPDDR5 memory IP for TSMC’s 5nm process

Complete DDR5/LPDDR5 memory IP for TSMC’s 5nm process

New Products |
By Nick Flaherty

Cadence Design Systems has launched a complete, silicon-proven IP design for DDR5 and LPDDR5 DRAM memory standards on TSMC’s N5 process.

The multi-standard IP was developed with Micron and includes the PHY and controller Design IP and Verification IP (VIP) for applications including data centre, storage, artificial intelligence/machine learning (AI/ML) and hyperscale computing on the latest 5nm chips.

Combining DDR5 and LPDDR5 protocols in the same memory interface IP offers a high-speed, scalable solution from large to small memory footprints. The aim is to make DDR5 and LPDDR5 implementation predictable on TSMC’s 5nm N5 process.

This allows users to use a single chip to support multiple memory types in different environments, enabling their chips to be used in different markets and products with different DRAM requirements, which is increasingly important with the rising costs at 5nm. 

“Designers of next-generation intelligent products require simple, efficient access to high-performance memory,” said Malcolm Humphrey, vice president and general manager of the core compute business for the Compute and Networking Business Unit at Micron. “Micron’s collaboration with Cadence and TSMC enables leading-edge memory interface IP on advanced technology nodes, empowering the ecosystem by bringing complete DDR5 and LPDDR5 DRAM memory solutions to the most advanced systems on chips.”

“We’re pleased to see the delivery of Cadence’s DDR5/LPDDR5 IP on the TSMC 5nm process technology, which is optimized for the latest emerging application areas,” said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “Through our continued collaboration with Cadence, we’re enabling mutual customers to design with these solutions, benefiting from the remarkable performance and power boost of our most advanced process technology and quickly launching their new product innovations to market.”

“As we continue to expand our collaboration with TSMC, our latest DDR5/LPDDR5 IP in TSMC’s 5nm process technology uniquely addresses the needs of next-generation data centre, AI/ML and hyperscale applications,” said Sanjive Agarwala, corporate vice president, R&D in the IP Group at Cadence. “Cadence IP solutions help customers simplify the design process so they can successfully deliver innovative, intelligent semiconductor products in a timely manner.”

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