Configurable embedded processor runs up to 2.2GHz
The 32-bit ARC HS34 and HS36 processors are the highest performance ARC processor cores to date, delivering 1.9 DMIPS/MHz at speeds up to 2.2 GHz. In a typical 28nm process the cores consume as little as 0.025mW/MHz in an area as small as 0.15mm2.
The optimization makes them ideally suited for the embedded and deeply embedded processors within system on chips (SoCs) for products such as solid-state drives, connected appliances, automotive controllers, media players, digital TV, set-top boxes and home networking products.
The HS family uses the ARCv2 instruction-set architecture (ISA) coupled with a new ten stage pipeline that supports out of order instruction retirement, minimizing idle processor cycles and maximizing instruction throughput. Sophisticated branch prediction and a late stage ALU improve the efficiency of instruction processing and allow a deterministic response for real time performance says Mike Thompson, Sr. Product Marketing Manager, ARC Processors and Subsystems.
To speed the execution of math functions, the ARC HS Processors give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a configurable IEEE 754-compliant floating point unit (single or double precision or both). The ARCv2-based cores provide an 18 percent improvement in code density compared to previous generation ARC cores, reducing memory requirements and support close coupled memory as well as instruction and data cache (HS36 only), with new 64-bit load-double/store-double and unaligned memory access capabilities that accelerate data transfers. Optional error-correcting code (ECC) hardware is available for all memories in the processor for applications that require a higher level of memory reliability and protection.
The highly-configurable ARC HS processors allow designers to tailor each instance of the core on their SoC for the optimum balance of performance, power and area. Users can define instruction extensions to the processor pipeline that enable the integration of their own proprietary hardware accelerators that can dramatically improve application specific performance while reducing power consumption and the amount of memory required. The configurable instructions are hidden from the operating systems to allow standard ports to be used.
Native ARM AMBA AXI and AHB standard interfaces are configurable for 32-bit or 64-bit transactions to optimize system throughput and SoC peripherals can be directly accessed by the CPU in a single cycle, minimizing system-level latencies and maximising hardware integration. By incorporating features to optimize the performance efficiency of both the processor and the system, the HS34 and H36 cores give designers the ability to create greater product differentiation while lowering the cost of implementation.
The new HS cores are supported by the Synopsys MetaWare Development Kit, a complete solution for developing, debugging, and optimising embedded software on ARC processors. The kit includes an optimised compiler to generate highly efficient code, a debugger for maximum visibility into the software and a fast instruction set simulator (ISS) for pre-hardware software development. A 100 percent cycle-accurate simulator is also available for design optimisation and verification. Operating system (OS) support for the HS Processor Family includes Synopsys’ MQX RTOS, a full-featured real-time operating system optimised for deterministic response times and memory size efficiency. Additional third-party hardware and software tools supporting software development on ARC HS processors are available from ARC Access Program partners include advanced debugging tools from Ashling Microsystems and Lauterbach and the popular ThreadX RTOS from Express Logic. A version of the core with an MMU to support embedded Linux is expected later s part of the development of the family.
“With more than 1.3 billion ARC-based chips shipping annually, we are keenly aware that each new generation of electronic devices requires processors to meet the conflicting goals of higher performance with lower power and smaller area, and that’s exactly what the ARC HS Processor Family delivers,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “The ARC HS34 and HS36 cores represent a significant advancement in the ARC portfolio and demonstrate Synopsys’ commitment to extending the ARC roadmap to meet designers’ evolving embedded requirements.”
"To keep pace with evolving market requirements in the digital TV market, our design teams are under constant pressure to deliver higher performance at lower power and cost points,” said Yves Mathys, CEO at Abilis Systems. “Synopsys’ ARC HS processors will enable us to achieve new levels of high performance and low power in our embedded designs with significant chip area savings. Leveraging ARC hardware and software development tools and third-party support will also help us keep our design schedules on track, which is critical as we introduce new digital media products.”
The DesignWare ARC HS34 and ARC HS36 processor cores and associated development tools are available immediately.
www.synopsys.com/arc
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