Configurable IP supports USB Type-C and USB 3.1, 3.0 and 2.0 specifications
The Type-C specification, often cited as the fastest-ramping interconnect specification to date, simplifies mechanical USB connectors with reversible cables (use either way round) , rotational symmetry (insert plug either way up), up to 10 Gbps data rate, bi-directional power delivery at configurable levels that can be as high as 100W, audio multiplexing and alternate modes such as DisplayPort and MHL. Synopsys’ DesignWare USB-C PHYs integrate Type-C functionality, reducing BOM costs by eliminating discrete multiplexers and crossbar switch components, which were previously required to support the small, reversible Type-C connector.
Synpopsys has introduced this IP first for 14/16-nm FinFET and 28-nm process points. The company says that the typical potential user looking to acquire IP for an SoC design will be adding the connectivity to a leading-edge and high-volume design, and will also, typically, be implementing it in a leading-edge technology.
Supporting the USB Type-C connector requires two SuperSpeed or Enhanced SuperSpeed datapaths, so designers could either implement two non-Type-C USB PHYs in a dual PHY solution or choose a single PHY that is optimised for Type-C. The DesignWare USB-C PHYs supporting USB 3.1, 3.0 and 2.0 offer an optimised solution with small (silicon) area and use up to 40% fewer pins (peripheral pinouts on an SoC die) than a dual PHY solution for Type-C.
The DesignWare USB-C PHYs are based on the established DesignWare USB PHY architectures that are shipping in volume in 28 nanometer (nm) and 14/16nm FinFET silicon, enabling designers to reduce system on chip (SoC) design risk when implementing the IP in advanced process technologies. The DesignWare USB-C PHYs are optimised for low power, meeting the stringent requirements of mobile devices such as smartphones and tablets, high volume consumer applications such as digital TVs, storage and networking applications.
The DesignWare USB-C 3.1 PHY offers 10 Gbps and 5 Gbps data transfer rates and consumes less than 55 mW power at 10 Gbps speeds. The DesignWare USB-C 3.0 PHY supports all USB 3.0 and 2.0 speed modes (SuperSpeed, High Speed, Full Speed and Low Speed) in a single design presented as GDSII files. Its USB PHY IP is, Synopsys says, already one of its most successful DesignWare lines. The company notes that the (former) offering supports the full USB 3.1 specification to 10 Gbit/sec, without using the Type-C connector, which it also expects to see becoming a significant product category.
“Teledyne-LeCroy and Synopsys have worked together for more than 15 years to perform early interoperability testing of new USB generations between our respective solutions,” said Mike Micheletti, product marketing manager at Teledyne-LeCroy. “Interoperability testing is critical to developing the USB 3.1 ecosystem, and the successful interoperability testing between DesignWare USB-C 3.1 and USB-C 3.0 IP and Teledyne-LeCroy’s Voyager M310C gives designers confidence that the IP will work as expected and reduce their design risk.”
The DesignWare USB-C PHYs are part of Synopsys’ complete USB solution, which also includes controllers, verification IP, IP Prototyping Kits and IP software development kits. Together, they reduce IP integration risk and speed time to market for consumer and mobile SoCs. The DesignWare USB 3.1 Controller IP, based on the DesignWare USB 3.0 Controller IP architecture which has shipped in more than 100 million SoCs, supports 10 Gbps data transfer rates, power saving capabilities and backward compatibility with existing USB 3.0 software stacks and device drivers. The DesignWare USB 3.1/3.0 IP Prototyping Kits and IP software development kits provide the essential hardware and software elements needed to reduce IP prototyping and integration effort, enabling designers to start implementing USB IP in an SoC in minutes. Synopsys USB Verification IP is based on a 100% SystemVerilog, UVM based architecture with test suites delivered as source code to enable quick development of a verification environment to verify the proper integration and connection of the USB interface within the SoC.
Synopsys; www.synopsys.com
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