Consortium formed to standardize chiplet ecosystem
Advanced Semiconductor Engineering, Inc., AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing Company have announced the formation of an industry consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem.
The organization, representing a diverse ecosystem of market segments, will address customer requests for more customizable package-level integration, connecting best-in-class die-to-die interconnect and protocols from an interoperable, multi-vendor ecosystem.
The founding companies also ratified the UCIe specification, an open industry standard developed to establish a ubiquitous interconnect at the package level. The UCIe 1.0 specification covers the die-to-die I/O physical layer, die-to-die protocols, and software stack which leverage the well-established PCI Express® (PCIe®) and Compute Express Link™ (CXL™) industry standards.
The UCIe 1.0 specification provides a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing to enable end users to easily mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) construction, including customized SoC.
The founding companies represent a wide range of industry expertise and include leading cloud service providers, foundries, system OEMs, silicon IP providers, and chip designers, and they are in the process of finalizing incorporation as an open standards body. Upon incorporation of the new UCIe industry organization later this year, member companies will begin work on the next generation of UCIe technology, including defining the chiplet form factor, management, enhanced security, and other essential protocols.
According to Dr. Lihong Cao, Director of Engineering and Technical Marketing at ASE: “The age of chiplets has truly arrived, driving the industry to evolve from silicon-centric thinking to system level planning and placing crucial focus on co-design of IC and package. UCIe will play a pivotal role in enabling ecosystem efficiencies, by lowering development time and cost through open standards for interfaces between various IPs within a multi-vendor ecosystem as well as utilization of advanced package level interconnect. There is broad industry recognition that Heterogeneous Integration will help bring chiplet-based designs to market.”
Cheolmin Park, Vice President of Memory Product Planning Team at Samsung Electronics adds: “Samsung envisions chiplet technology becoming necessary for performance gains in computing systems as process nodes continue to scale, with dies inside each package eventually communicating through a single language. We expect the UCIe Consortium to foster a vibrant chiplet ecosystem and establish the framework for a viable open-standard interface industry-wide. As a total solutions provider for memory, logic, and foundry, Samsung anticipates spearheading consortium efforts to further identify the best ways for enhancing system performance through chiplet technology.”
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