Paralleling power MOSFETs in high-current applications

Paralleling power MOSFETs in high-current applications

By Wisse Hettinga

Effect of MOSFET parameter mismatch on current distribution and power dissipation imbalance

Medic Urban, Senior Application Engineer, Infineon Technologies

When several power MOSFETs are connected in parallel to increase the overall system current capability, it is often assumed that the current is equally distributed or equally shared between the paralleled devices. However, several characteristics of the PCB layout and specific MOSFET parameters can influence this distribution and cause imbalance to the current sharing whenever the parameters are not perfectly matched or if the layout is not perfectly symmetrical.

This article discusses the MOSFET parameters playing an essential role in the current sharing and addresses how design engineers can assess the required margin of output current capability for parallel MOSFET designs by evaluating the excess power losses incurred in the MOSFET that carries more current. The examples shown in this article refer to a half-bridge-based application, where MOSFETs are connected in parallel, as depicted in Figure 1.

Figure 1. Simplified half-bridge schematic with paralleled MOSFETs

MOSFET parameters influencing current distribution
When mismatched, specific MOSFET parameters influence how current is distributed among the paralleled devices in various ways. The value of RDS(on) has an effect during the conduction of the MOSFETs, while some other parameters (VGS(th), RG, CGS, CGD) influence current sharing during switching (see Table 1 [1] and read the related Application Note (see end of article) for full details).

Table 1 Parameters playing a significant role in current-sharing [1]

Quantifying the effect of mismatched MOSFET parameters on current and power dissipation imbalance
To compare the relevance of particular MOSFET characteristics or parameters to the overall system performance, their effect on performance needs to be quantified in a way that is most relevant for the given application.

Current sharing imbalance means that some devices conduct higher than average currents. This results in a higher than average power dissipation and consequently a higher maximum component temperature, with regard to the temperatures resulting from estimates that assume perfect current sharing and equal component power dissipation.

Figure 2 shows the power losses of the MOSFET with the highest dissipation, which, in this case, is the MOSFET with the lowest VGS(th). The different lines represent different VGS(th) mismatches used in our simulations [1]. ΔVGS(th) = 1.6 V refers to the case when the VGS(th) of Q1 is 1.6 V lower than the VGS(th) of Q3 when Q1 and Q3 are used in parallel (Figure 1).

Figure 2. Average power dissipation at the hottest MOSFET [1]


Assuming the thermal characteristics of the MOSFETs are the same, the MOSFET with the highest dissipation will always turn out to be the hottest one. The increased power dissipation and the excess component temperatures will therefore limit the maximum system performance. In this case, a certain amount of oversizing is necessary, which means that additional MOSFETs need to be added in parallel so that the system can meet the design requirements.

The temperatures of the MOSFET with the highest dissipation (i.e., the hottest one) are plotted in Figure 3. Those apply to an example with a heatsink temperature of Ths = 80°C. To make use of this graph, one must observe the output current at a particular device temperature. For example, if the system requirements allow for the maximum Tj(max) = 100°C, the output current will be limited accordingly.

Figure 3. Temperature of the hottest MOSFET vs. output current (2 MOSFETs in parallel)

The resulting distribution of average power dissipation between the paralleled MOSFETs depends on the current distribution but is also affected by the nature of the output load current and the applied switching modulation.

For example, in motor drive applications, the output of each half-bridge is a sinusoidal current, and the resulting power dissipation differs from DC applications. Space vector modulation (SVM) and sinusoidally-weighted pulse width modulation (SPWM) are the typical modulation methods of driving the sinusoidal output currents [1]. A similar analysis can be performed for different applications utilizing various modulation techniques.

This article shows an example of what a design engineer needs to consider in order to size his system by taking into account not only the “typical” (i.e., ideal) performance but also realistic circumstances caused by inevitable component parameter variation.

Read the extensive Application Note to gain more insights and browse examples as well as test results. Additionally, check out the available online training and please make sure to visit Infineon’s Power MOSFET webpage.

[1] App note: AN_2009_PL18_2010_105641, “Paralleling power MOSFETs in high current applications,” Infineon Technologies, May 2021
[2] App Note: AN_1803_PL11_1804_092613, “Paralleling MOSFETs in high-current LV drive applications,” Infineon Technologies, April 2018.
[3] Forsythe B. James, “Paralleling of power MOSFETs for higher power output,” Article, International Rectifier, March 2006



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