Controller IP for 800G Ethernet chips designs
Cadence Design Systems has developed a High-Speed Ethernet Controller IP family which enables complete Ethernet subsystem solutions up to 800G when used with Cadence SerDes PHY IP in 7nm, 5nm and 3nm process nodes.
The controller family supports different aggregated bandwidths for 100G, 200G, 400G and 800G Ethernet supports both single- and multi-Ethernet channel designs with compliance to the IEEE 802.3 and Ethernet Technology Consortium specifications.
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The IP provides full-featured media access control (MAC), physical coding sublayer (PCS), forward error correction (FEC) and physical medium attachment (PMA) blocks for a complete architecture. It also integrates FEC support, including RS(528,514), RS(544,514), Firecode and Ethernet Technology Consortium Low Latency RS FEC.
This allows designs to choose the best option for different application requirements in cloud interconnect, artificial intelligence and machine learning (AI/ML), and 5G infrastructures.
The latest PCI Express 6.0 technology is also aiming at data centre, AI and ML chip designs (see links below).
The controller is design to work with the Cadence 112G/56G and other Ethernet SerDes PHY IP with full subsystem deliveries with integrated PHY and controller to ease integration and streamline system on chip designs. The IP is already silicon proven in AI/ML customer applications.
“The exploding bandwidth demand from cloud, AI/ML and 5G has driven Ethernet protocols to evolve and has accelerated 800G market adoption,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “Cadence continues to invest in design and interface IP that addresses our customers’ rapidly evolving requirements. The Cadence high-speed Ethernet subsystem solutions with best-in-class PHY and feature-rich controller IP further solidify our leadership position with high-performance connectivity IP offerings.”
www.cadence.com/go/hsethernetcontroller
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- Intel updates ATX power for PCIe 5.0
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