‘Correct by construction’ tool for chip power layout down to 2nm

‘Correct by construction’ tool for chip power layout down to 2nm

New Products |
By Nick Flaherty

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Siemens Digital Industries Software has developed a chip power design tool that can boost the design and reliability with a ‘Correct by construction’ approach down to 2nm.

Calibre DesignEnhancer automatically implements design layout modifications for power routing, IR voltage drop and electromigration much earlier in the IC design and verification process on designs from 130nm down to 2nm.

Before conducting physical verification on an IC design, engineers have traditionally relied on third-party P&R tools to incorporate design for manufacturing (DFM) optimizations, often requiring multiple time-consuming runs before converging on a clean version for the design rule checks. The new tool aims to shorten this DRC-clean process and reduce EM/IR issues while preparing a layout for physical verification.

The Calibre DesignEnhancer tool supports via modification automatically analyzes layouts and inserts up to 1 million+ Calibre-clean correct-by-construction vias to reduce the impact of via resistance on EM/IR and reliability. Because these modifications are based on a thorough understanding of the layout and signoff design rules, via insertion can help customers meet their power goals without impacting performance or area metrics.

Power/ground enhancements automatically analyze layouts and insert Calibre nmDRC-clean vias and interconnects in open tracks to create parallel runs that can lower resistance on power/ground structures and reduce IR and EM issues associated with the power grid. Customers using the Calibre DesignEnhancer tool have achieved up to 90 percent reductions in IR drop issues.

Filler cell insertion optimizes the insertion of decoupling capacitor (DCAP) and filler cells required for physical verification readiness. It replaces traditional P&R filler cell insertion processes, which helps to provide better quality of results and up to 10X faster runtimes.

“The Calibre DesignEnhancer solution is proving to be extremely useful in our continuous efforts to enhance our IC design processes, for example, by addressing and resolving specification resistance and IR-drop issues,” said Pier Luigi Rolandi, Smart Power Technology R&D Design Enablement Director, STMicroelectronics.

“In today’s challenging IC design environment, engineering teams working at advanced nodes are struggling to optimize layouts for manufacturability and performance within the given area and project timeline constraints in which they must work,” said Michael White, Senior Director, Physical Verification Product Management, Calibre Design Solutions, Siemens Digital Industries Software. “By using the Calibre DesignEnhancer software, designers can bring Calibre polygonal processing speed and accuracy into play earlier in the design cycle, which can help to avoid late design cycle surprises.”

The Calibre DesignEnhancer solution uses proven technology, engines, and qualified rule decks from Calibre, all of which can help customers generate results that are correct by construction, Calibre DRC-clean, and ready for signoff verification. It can read OASIS, GDS, and LEF/DEF as input files, and output layout modifications in any combination of OASIS, GDS, or incremental DEF files, helping design teams to back-annotate Calibre DesignEnhancer software changes to the design database for power and timing analysis using commonly preferred tools for further analysis earlier in the design creation lifecycle.

The Calibre DesignEnhancer tool is part of the Calibre nmPlatform for IC physical verification and integrates with all major design and implementation environments using industry interface standards, providing a user-friendly environment that requires minimal training and setup.

Calibre DesignEnhancer kits are available now for all leading foundries supporting designs from 130nm to 2nm, depending on the use model and the technology.

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