Correlator IP for FPGA detects patterns across thousands of data streams

Correlator IP for FPGA detects patterns across thousands of data streams

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By eeNews Europe

The core provides the ability to simultaneously analyse thousands of input channels obtained from different carriers in real time using advanced parallel processing. It can search for up to two Unique Patterns (UPs) on each channel and provides reliable identification with a low False Alarm Rate. The Correlator AX uses both cross-correlation and auto-correlation techniques to provide maximum performance.

Dr Alex Kuhrt, RFEL’s CEO, said: “There are many applications where you are looking for a particular signal in amongst the noise – the classic looking for a needle in a haystack. The Correlator AX is designed to automate this process with advanced pattern recognition techniques to look for several UPs across a number of input channels in real time, with sample rates up to 128 Msps (Mega samples per second). Each UP can be up to 1024 words long. This makes it a solution for big data searches, electronic warfare signal detection, cyber monitoring, communications, instrumentation, 1-D image correlation and Physics research such as radio telescopes.”

Correlator AX IP is designed to interface directly with RFEL’s ChannelCore Flex to provide a seamless, high performance solution for signal processing and detection. Both are highly optimised by RFEL to run on the minimum FPGA real estate to balance performance against cost and power consumption.

Advanced features include partitioned correlation to mitigate frequency errors, cross correlation with user-defined UPs, and auto-correlation is provided to normalise the cross-correlation result so that the detection process is governed by only the pattern of the input sequence and not by its overall power level. Cross-correlation is performed by continuously assessing the channel input data stream (sample-by-sample) with the expected UP. The output consists of the interleaved channel data and time-aligned correlation coefficients. Oversampled data streams can be supported for communications applications.

The Correlator AX core will be available in Q1 2016, with initial support for Xilinx 5, 6, 7 and Ultrascale families with Altera to follow. Parameters can be adjusted to suit a user’s particular requirements. The Correlator AX is supported by a detailed bit-true MATLAB model of the processing.


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