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Cortus’ 32-bit processor cores displace 8-bit solutions in smart cards

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By eeNews Europe

These two new cores are the company’s first products based on its v2 instruction set, a subset of v1 aimed at reducing the size of a system’s instruction memory. APS23 will find its way into low power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart.

“We have focused on reducing the size of the instruction memory which is usually the largest single component in a system and are seeing an average 16% improvement in code density over our earlier (v1) cores”, told us Mr. Michael Chapman, CEO and President of Cortus.

With the v1 instruction set, Cortus’ 32-bit APS5 processor core had the equivalent code density of a Cortex M3 from ARM, but that’s further improved with the v2 instruction set on Cortus’ new APS25.

The company also claims the core is smaller and more energy efficient, and that thanks to using a different pipeline length, the core could run these instructions at 2.5 times the maximum frequency of that of its more expensive competitor.

“Too good to be true! Engineers who are not yet our customers just won’t take our word for it”, commented Chapman, “until they get an evaluation kit and can perform their own measurement”.

“Typically, once a company is entrenched using ARM, it is very difficult to convince them, but for very specialized applications and for highly secure use cases, a lot of medium-sized companies come to us. Then, last March we have opened an office in Korea to expand our customer support in Asia, a year after we opened our US office, and our contacts there have exploded, especially so because ARM is not providing proper customer service in Asia”, Chapman continued.

“Just as an example of cost-efficiency, in the SIM card industry, the Samsung 8-bit solution is being displaced by a solution designed by StarChip (now a Morpho subsidiary) incorporating our 32-bit core, because the overall chip cost is lower. By adopting our solution, Morpho gained 18% in margin, yet enabling their SIM cards with a more powerful and more secure processor”, Chapman said.


The APS23 has a Harvard architecture, sixteen 32-bit registers, a 3-stage pipeline and a sequential multiplier. It supports the AXI4-Lite bus as well as Cortus APS peripherals. The core delivers 2.83 DMIPS/MHz and 1.44 CoreMarks/MHz in computational performance. The minimal usable APS23 CPU starts around 9.8 kgates when optimised for area. Dynamic power is 12 microwatts/MHz with a 90 nm process (Cortus cores are synthesisable and foundry independent).

Optimized for multi-core implementations in connected devices, the APS25 IP core is aimed at embedded systems demanding greater computational performance and system complexity while also requiring maximum code density and extendibility.

It supports the use of coprocessors or symmetric multiprocessing. The APS25 has a Harvard architecture, sixteen 32-bit registers, a 5-stage pipeline, a sequential multiplier. It supports the AXI4 bus as well as Cortus APS peripherals.

Up to eight co-processors can be added to an APS25 core. What’s more, the Cortus coprocessor interface allows licensees to add custom coprocessors, for example to accelerate computations in cryptography or signal processing, without knowing details of the internals of the core. Co-processor instructions can be inserted into C-code appearing as function calls.

The small size of APS25 makes it highly suitable for applications requiring two cores. For example a common approach in functional safety is for two cores to execute the same code in lock step and to trigger an alarm if the results do not match. Another application is secure execution where it is desirable to physically separate the execution of secure software by running it on a supervisory CPU while application code runs on another CPU core.

The Cortus v2 instruction set allows the seamless mixing of 16-, 24- and 32-bit instructions without mode switching. This instruction set is richer than the v1 instruction set which used a mix of 16- and 32-bit instructions.

Cortus will continue to offer products based on the v1 instruction set (e.g. APS3R) in parallel with the new cores based on the v2 instruction set. All C/C++ or assembler code developed for the v1 cores can be used unmodified on the v2 cores.

All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure, which ensures rapid, real time interrupt response, with low software overhead. The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OSII.

Visit Cortus S.A.S. at www.cortus.com

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