Cryo memory test chip tapes out for quantum computers

Cryo memory test chip tapes out for quantum computers

Technology News |
By Nick Flaherty

A UK project has taped out a demonstration chip with cryogenic memory IP for quantum computer control systems.

The Innovate UK project is led by ultra-low power memory IP developer SureCore which has developed embedded SRAM cryogenic memory IP that can operate from 77K (-196°C) down to the near absolute zero to address a wide range of different quantum computer architectures.

Both standard cell and IO cell libraries for the SRM have been re-characterised for operation at cryogenic temperatures, enabling an industry standard RTL to GDSII physical design flow to be used for chip designs.

The project, the “Development of CryoCMOS to Enable the Next Generation of Scalable Quantum Computers”, aims to address the challenges to quantum computer scaling that come needing the increasingly complex control electronics close to the qubits at cryogenic temperatures in a cryostat.

This requires the control chip power consumption to be as low as possible to ensure that excess heat is kept to a minimum so that it does not cause additional thermal load on the cryostat. Current quantum computer designs have the control electronics located outside the cryostat as modern semiconductor technology is only qualified to work down to -40°C. As the temperature is reduced close to absolute zero, the operating characteristics of the transistors change significantly.

Besides sureCore, the project includes Synopsys, SemiWise, Oxford Instruments, SeeQC, Universal Quantum and the University of Glasgow. The project has been measuring, understanding and modelling this behavioural change over the past months to develop the demonstration chip.

The modelling work is being undertaken by SemiWise and the QC research group at the University of Glasgow. Synopsys uses the data generated to refine its TCAD tools. A combination of measurements and simulation data for the cryogenic memory IP have been used by SemiWise to re-centre a foundry PDK for cryogenic temperatures and to enable the cryogenic circuit design.

“Currently, expensive bulky cabling connects room temperature control electronics to the qubits housed in the cryostat. Enabling QC developers to be able to exploit the fabless design paradigm and create their own custom cryogenic control SoCs, which can be housed with the qubits inside the cryostat, is a game-changer that will rapidly enable QC scaling. Immediate benefits include cost, size and, most importantly, latency reduction,” said Paul Wells, CEO of sureCore in Sheffield.

“The next step will be characterising the demonstrator chip at cryo temperatures to further refine and validate the models to help improve the performance. We are positioning ourselves as the go-to experts in the field of cryogenic IP development and, along with our consortium partners, we are enabling the UK to be seen as a centre of excellence for QC,” he said.

One consortium member is Universal Quantum (UQ), which has developed a modular ion-trap quantum computer hardware architecture that will directly benefit from the cryogenic IP developed by the project.;;

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