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Crypto & OS support boosts Cortus’ processor IP in home automation

Crypto & OS support boosts Cortus’ processor IP in home automation

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By Graham Prophet



Optimised cryptography support is now in place on the 32-bit Cortus APS3RP core, from Swiss company Oberon microsystems, whose offering yields fast cryptographic performance and small memory footprint on the Cortus IP. Oberon’s cryptographic code is a component of its OberonHAP product, and has been ported to and optimised for the Cortus APS3RP 32-bit IP core – including writing critical sections in assembly language for efficiency. Small memory footprint and minimalist processor core is well suited to secure ASICs in battery-powered home automation devices.

 

Oberon microsystems has developed, analysed and optimised the cryptographic code of OberonHAP since 2013. It has developed – and verified by use of formal mathematical analysis – novel algorithm combinations, leading to its claims of code three times as fast as a good implementation in C. OberonHAP thus makes secure home automation feasible even on low-power, low-cost 32-bit microcontroller cores for ASICs.

OberonHAP implements the following cryptographic algorithms for pairing, authentication and encryption: Secure Remote Password (SRP); Ed25519; Curve25519; HKDF-SHA-512; and ChaCha20-Poly1305. For an integrated circuit with the processor core running at 50 MHz, the cryptographic processing of the SRP algorithm – which is required once in the lifetime of a home automation device – takes less than five seconds. Cryptographic processing during opening of a session between a device and a smartphone takes less than 100 milliseconds. RAM requirements were brought down to 2.5 kB.

 

The APS3RP is an enhanced performance version of the APS3R and provides a single cycle parallel multiplier. It has a Harvard architecture and a 3-stage pipeline. The Cortus family of APS processors offers a wide choice of computational performance and system complexity for embedded SoCs. All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.

 

To expand its OS and IDE offering – which already includes its APS toolchain and IDE (for C and C++), and ports of various RTOSs such as FreeRTOS, Micrium μC/OSII, Micrium μC/OSIII, Cortus has now added Blunk’s TargetOS.

Blunk Microsystems is offering turnkey demo packages for Cortus cores. Advancing its support of the Cortus APS processor family beyond the kernel port completed in 2015, Blunk has integrated the Cortus OpenOCD debug solution with its CrossStep IDE for embedded development and provides verified drivers and protocol stacks for Cortus’ I/O peripherals.

 

Turnkey demos for the Cortus instruction set simulator (ISS) and XC6SLC development board can be downloaded from www.CrossStep.com. These downloads include Blunk’s free lite kernel and a free license to the CrossStep IDE. The demos support evaluation of Blunk’s middleware components, including file systems (with full coverage for all flash memory types), TCP/IP networking stack (with certified IPv6 support), USB stack, graphics library, and embedded web server.

 

Blunk Microsystems; www.blunkmicro.com

 

Oberon microsystems; www.oberon.ch and https://oberonhap.com/about/

 

Cortus; www.cortus.com

 

 

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