CSEM pens Deeply Depleted Channel development deal

CSEM pens Deeply Depleted Channel development deal

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By Field Editor

The agreement encompasses the development of ultra-low voltage, ultra-low power standard cell libraries, power management cells and memories as well as the development of a representative qualification vehicle to showcase the technology, and will include cross-licensing of related IP.

For wearable and IOT devices superior energy efficiency is crucial: the conflicting requirements of increased miniaturization along with longer battery life mean that standard CMOS technologies are reaching their limits and that new solutions are urgently needed. Since the power consumption of digital circuits is proportional to the square of the supply voltage, low voltage operation is the best hope for significant improvements while maintaining NRE costs in check.

MIFS’ Deeply Depleted Channel (DDC) technology enables fabrication of extremely-low-leakage transistors operating at supply voltages (Vdd) below 0.5 V to obtain maximum power efficiency. DDC offers a better Vt mismatch & spread than conventional CMOS, allowing lower Vdd with minimum degradation of performance. Applying DDC to 40/55 nm CMOS along with mixed signal/RF and embedded NVM allows cost-effective and highly integrated analog and RF SoCs for IoT /wearable platforms. MIFS has now joined forces with CSEM, with their long design experience in low-voltage, low-power integrated circuits, to develop an ultra-low power IP platform targeting near/sub-threshold supply voltages in the MIFS DDC technology. The goal is to develop a best-in-class Extreme-Low Power (ELP) platform with the associated ecosystem to enable chip designs for energy-critical wearable and IOT devices.

“MIFS DDC technology offers best-in-class low voltage and low leakage operation. By working with CSEM we will be able to develop an ecosystem to make the benefits of this technology available widely to our partners,” said Masahiro Chijiiwa, Director of MIFS and Corporate Senior VP.

The development will be performed in close direct collaboration between process engineers, library specialists and ULP design experts, both in Japan and Europe, in order to unleash the full potential of the new platform, which is expected to be available for limited release in Q4 2016

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