It does so by reintroducing a more fine-grained and visual approach to layout by way of a series of design assistants that provide visually-assisted automation.
Synopsys declined to put a figure on the speed up factor the software produces.
FinFET complexity is dragging IC design productivity away from its historical linear progress. Source: Synopsys.
The need to introduce a novel compiler is driven by increased complexity. Layout rules at 10nm are approximately 3 times more complex then they were at 40nm and with FinFETs single devices that could simply be scaled in area become arrays of fins. Electromigration and IR drop calculations are more difficult and layout restrictions make engineering change orders harder to implement, Synopsys claims.
A second and more important reason is that constraint-driven layout, the paradigm of the previous generations of design takes a long time and can produce “take it or leave it” trial layouts that are sub-optimal. For analog and mixed-signal and transistor block designs layout can be very visual.
The design assistants include: Template Assistants that help designers reuse existing custom layout know-how; In-Design Assistants that reduce iterations with native design rule checks and parasitic extraction; Layout Assistants that speed up layout tasks with user-guided placement and routing; and Co-Design Assistants unify that custom and digital flow to accelerate mixed-signal IC design.
“We asked the Custom Compiler development team to focus on improving FinFET layout productivity because we saw large increases in the layout effort across a wide range of IP development projects, from standard cells to high-performance SerDes,” said Joachim Kunkel, executive vice president and general manager of the Solutions Group at Synopsys, in a statement. “Custom Compiler’s Layout Assistants allowed us to implement a novel layout methodology that reduces the time of many layout tasks from hours to minutes.”
Custom Compiler is based on the industry-standard Open Access Database. TSMC has certified Custom Compiler for use on its 10nm and 7nm manufacturing process technologies and STMicroelectronics has adopted Custom Compiler for 28nm FDSOI standard cell and memory layout.
Related links and articles: