Custom eFPGA blocks supercharge data acceleration systems
Speedcore eFPGAs deliver the highest-performance and lowest-cost hardware acceleration, claims Achronix, with Speedcore custom blocks now allowing functions that traditionally ran slowly and consumed significant resources in standalone FPGA fabrics to be optimised for maximum performance and minimal die area. The company claims that thanks to its Speedcore custom blocks, the area of a CNN-based YOLO object recognition algorithm was reduced by over 40% by optimising the DSP and memory blocks for matrix multiplication. As another acceleration example, large string search functions that require parallel comparator arrays were shrunk by over 90% in die area when implemented in Speedcore custom blocks.
Barrel shifters and bit manipulation structures can be fully implemented in Speedcore custom blocks allowing larger, sophisticated applications in the same area and increasing achievable frequency. The core functionality of a 400 Gbps packet processing data-path running at 800 MHz is implemented in Speedcore custom blocks with the programmable logic managing the analysis and control functionality. Today’s standalone FPGAs cannot support this high throughput for packet processing applications.
Speedcore custom blocks are defined collaboratively by Achronix with its customers through a detailed architecture analysis of acceleration workloads. Repeated functions that are performance and/or area bottlenecks are evaluated as candidates to be hardened into Speedcore custom blocks.
A new release of ACE design tools that includes the new Speedcore eFPGA with custom blocks is then provided to customers for benchmarking and evaluation. If required, the process is iterated to create the optimal solution for the customer’s system.
Achronix ACE design tools fully support Speedcore custom blocks from design capture to bitstream generation and system debug in the same way as memories and DSP blocks. Achronix creates a unique GUI for each Speedcore custom block that manages all configuration rules. ACE contains full timing details for all configurations of the Speedcore custom blocks, which allows ACE to complete timing-based place-and-route for designs.
Customers can use the powerful Floorplanner tool for design optimisation, and to make regional or site assignments for all block instances. ACE also includes a critical path analysis tool that allows customers to analyse timing. Customers can also use ACE’s powerful SnapShot embedded logic analyser to create complex triggers and show run-time signals within Speedcore.
Speedcore is embedded FPGA (eFPGA) IP that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Speedcore look-up-tables (LUTs), RAM blocks, DSP64 blocks and custom blocks can be assembled in flexible columns to create the optimal programmable function for any given application.
Achronix – www.achronix.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
