Custom instruction set EDA tool builds high performance image processing DSP

Custom instruction set EDA tool builds high performance image processing DSP

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By eeNews Europe

Synopsys’ ASIP design tools enabled rapid exploration and optimisation of processor architectures; Kyocera created a custom high performance DSP in less than a year, and automated creation of software development kit (SDK) and RTL design reduced engineering effort by about 75% compared to traditional manual processes.

By using tools that automate the design and optimisation of application specific processors, Kyocera was able to develop a custom DSP that delivers the high performance required for complex image processing functions in less than a year; unlike fixed hardware, the resulting ASIP provides the programmability and flexibility to meet the needs of multi-function printer image processing functions.

According to Michihiro Okada, general manager of the Software 3 R&D Division, Corporate Software Development Division at Kyocera Document Solutions, "Being able to use a single processor description to design highly efficient RTL as well as the associated software development kit, including an optimising C compiler, allowed us to focus on optimising our architecture throughout the entire design process."

Traditionally, each Kyocera multi functional printer model required the development of model-specific, fixed hardware system on chips (SoCs) to meet unique image processing algorithms and performance specifications. To improve development efficiency and lower total cost of ownership over the life of its next generation printer products, Kyocera required a more flexible and higher performance processor design with full programmability. After determining commercially available DSPs would not meet their performance goals, they selected Synopsys’ ASIP design tools to develop their own custom processor.

The ASIP solution from Synopsys enabled Kyocera to use a high level specification and quickly model multiple processor architectures, profile performance, and tune the architecture for their specific image processing application. Using this single input specification, Synopsys’ tool automatically generated the software development kit containing the instruction set simulator (ISS), assembler, linker, debugger and C compiler, as well as the synthesisable RTL design. This enabled early software development and debugging, as well as saving Kyocera time and effort in creating the SDK and RTL. The combination of early SDK availability and automation of architecture exploration and design creation resulted in a significant reduction in KYOCERA’s overall project schedule while producing a design optimised for their specific performance.

"By replacing fixed hardware with ASIPs, companies can save significant development effort and achieve their aggressive project schedules," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. A fuller description of the tools application is at


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